arm64: dts: r8a7795: Add L2 cache-controller nodes
authorGeert Uytterhoeven <geert+renesas@glider.be>
Sat, 16 Jan 2016 14:17:36 +0000 (15:17 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Fri, 5 Feb 2016 09:43:42 +0000 (10:43 +0100)
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a7795.dtsi

index 9634e3a..3f00e85 100644 (file)
@@ -39,6 +39,7 @@
                        compatible = "arm,cortex-a57", "arm,armv8";
                        reg = <0x0>;
                        device_type = "cpu";
+                       next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
                };
 
                        compatible = "arm,cortex-a57","arm,armv8";
                        reg = <0x1>;
                        device_type = "cpu";
+                       next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
                };
                a57_2: cpu@2 {
                        compatible = "arm,cortex-a57","arm,armv8";
                        reg = <0x2>;
                        device_type = "cpu";
+                       next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
                };
                a57_3: cpu@3 {
                        compatible = "arm,cortex-a57","arm,armv8";
                        reg = <0x3>;
                        device_type = "cpu";
+                       next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
                };
        };
 
+       L2_CA57: cache-controller@0 {
+               compatible = "cache";
+       };
+
        extal_clk: extal {
                compatible = "fixed-clock";
                #clock-cells = <0>;