2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+ * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code
+ generation for -maltivec=be.
+ (altivec_vsumsws): Simplify redundant test.
+
+2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
* altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec.
(UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise.
(UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise.
"vsum4s<VI_char>s %0,%1,%2"
[(set_attr "type" "veccomplex")])
+;; FIXME: For the following two patterns, the scratch should only be
+;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should
+;; be emitted separately.
(define_insn "altivec_vsum2sws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM2SWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+ (clobber (match_scratch:V4SI 3 "=v"))]
"TARGET_ALTIVEC"
- "vsum2sws %0,%1,%2"
- [(set_attr "type" "veccomplex")])
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vsum2sws %0,%1,%2";
+ else
+ return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4";
+}
+ [(set_attr "type" "veccomplex")
+ (set (attr "length")
+ (if_then_else
+ (match_test "VECTOR_ELT_ORDER_BIG")
+ (const_string "4")
+ (const_string "12")))])
(define_insn "altivec_vsumsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(clobber (match_scratch:V4SI 3 "=v"))]
"TARGET_ALTIVEC"
{
- if (BYTES_BIG_ENDIAN || VECTOR_ELT_ORDER_BIG)
+ if (VECTOR_ELT_ORDER_BIG)
return "vsumsws %0,%1,%2";
else
return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvspltw %0,%3,3";
[(set_attr "type" "veccomplex")
(set (attr "length")
(if_then_else
- (match_test "(BYTES_BIG_ENDIAN || VECTOR_ELT_ORDER_BIG)")
+ (match_test "(VECTOR_ELT_ORDER_BIG)")
(const_string "4")
(const_string "12")))])
2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+ * gcc.dg/vmx/sum2s.c: New.
+ * gcc.dg/vmx/sum2s-be-order.c: New.
+
+2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
* gcc.dg/vmx/pack.c: New.
* gcc.dg/vmx/pack-be-order.c: New.
* gcc.dg/vmx/unpack.c: New.
--- /dev/null
+/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
+
+#include "harness.h"
+
+static void test()
+{
+ vector signed int vsia = {-10,1,2,3};
+ vector signed int vsib = {100,101,102,-103};
+ vector signed int vsir;
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ vector signed int vsier = {91,0,107,0};
+#else
+ vector signed int vsier = {0,92,0,-98};
+#endif
+
+ vsir = vec_sum2s (vsia, vsib);
+
+ check (vec_all_eq (vsir, vsier), "vsir");
+}
--- /dev/null
+#include "harness.h"
+
+static void test()
+{
+ vector signed int vsia = {-10,1,2,3};
+ vector signed int vsib = {100,101,102,-103};
+ vector signed int vsir;
+ vector signed int vsier = {0,92,0,-98};
+
+ vsir = vec_sum2s (vsia, vsib);
+
+ check (vec_all_eq (vsir, vsier), "vsir");
+}