Improve feenableexcept performance - avoid an unnecessary FPCR read in case

the FPCR does not change. Also improve the logic of the return value.

diff --git a/ChangeLog b/ChangeLog
index ecf9d7b..d013561 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,10 @@
 2015-08-05  Wilco Dijkstra  <wdijkstr@arm.com>
 
+       * sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept):
+       Optimize to avoid an unnecessary FPCR read.
+
+2015-08-05  Wilco Dijkstra  <wdijkstr@arm.com>
+
        * sysdeps/aarch64/fpu/fesetenv.c (fesetenv):
        Optimize to reduce FPCR/FPSR accesses.
 

diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index 82ed0b6..a0f736c 100644 (file)
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -24,24 +24,22 @@ feenableexcept (int excepts)
 {
   fpu_control_t fpcr;
   fpu_control_t fpcr_new;
+  fpu_control_t updated_fpcr;
 
   _FPU_GETCW (fpcr);
   excepts &= FE_ALL_EXCEPT;
   fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
 
   if (fpcr != fpcr_new)
-    _FPU_SETCW (fpcr_new);
-
-  /* Trapping exceptions are optional in AArch64 the relevant enable
-     bits in FPCR are RES0 hence the absence of support can be
-     detected by reading back the FPCR and comparing with the required
-     value.  */
-  if (excepts)
     {
-      fpu_control_t updated_fpcr;
+      _FPU_SETCW (fpcr_new);
 
+      /* Trapping exceptions are optional in AArch64; the relevant enable
+        bits in FPCR are RES0 hence the absence of support can be detected
+        by reading back the FPCR and comparing with the required value.  */
       _FPU_GETCW (updated_fpcr);
-      if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+
+      if (fpcr_new & ~updated_fpcr)
        return -1;
     }