arm64: dts: qcom: sm8450: add PCIe0 RC device

Add device tree node for the first PCIe host found on the Qualcomm
SM8450 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220301061500.2110569-3-dmitry.baryshkov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index cd88115..d79ad52 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -754,6 +754,81 @@
                        };
                };
 
+               pcie0: pci@1c00000 {
+                       compatible = "qcom,pcie-sm8450-pcie0";
+                       reg = <0 0x01c00000 0 0x3000>,
+                             <0 0x60000000 0 0xf1d>,
+                             <0 0x60000f20 0 0xa8>,
+                             <0 0x60001000 0 0x1000>,
+                             <0 0x60100000 0 0x100000>;
+                       reg-names = "parf", "dbi", "elbi", "atu", "config";
+                       device_type = "pci";
+                       linux,pci-domain = <0>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <1>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                       <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                       <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                       <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                       clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+                                <&pcie0_lane>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+                       clock-names = "pipe",
+                                     "pipe_mux",
+                                     "phy_pipe",
+                                     "ref",
+                                     "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "ddrss_sf_tbu",
+                                     "aggre0",
+                                     "aggre1";
+
+                       iommus = <&apps_smmu 0x1c00 0x7f>;
+                       iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
+                                   <0x100 &apps_smmu 0x1c01 0x1>;
+
+                       resets = <&gcc GCC_PCIE_0_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc PCIE_0_GDSC>;
+                       power-domain-names = "gdsc";
+
+                       phys = <&pcie0_lane>;
+                       phy-names = "pciephy";
+
+                       perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+                       wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pcie0_default_state>;
+
+                       status = "disabled";
+               };
+
                pcie0_phy: phy@1c06000 {
                        compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
                        reg = <0 0x01c06000 0 0x200>;
@@ -1208,6 +1283,29 @@
                        gpio-ranges = <&tlmm 0 0 211>;
                        wakeup-parent = <&pdc>;
 
+                       pcie0_default_state: pcie0-default-state {
+                               perst {
+                                       pins = "gpio94";
+                                       function = "gpio";
+                                       drive-strength = <2>;
+                                       bias-pull-down;
+                               };
+
+                               clkreq {
+                                       pins = "gpio95";
+                                       function = "pcie0_clkreqn";
+                                       drive-strength = <2>;
+                                       bias-pull-up;
+                               };
+
+                               wake {
+                                       pins = "gpio96";
+                                       function = "gpio";
+                                       drive-strength = <2>;
+                                       bias-pull-up;
+                               };
+                       };
+
                        qup_i2c13_data_clk: qup-i2c13-data-clk {
                                pins = "gpio48", "gpio49";
                                function = "qup13";