arm: dts: zynq: Add Digilent ZYBO board

Add a DTS describing the Digilent ZYBO board. Similar to ZED but with
a 50MHz crystal instead of 33MHz.

Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89ca..db51dbd 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -489,7 +489,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
        zynq-parallella.dtb \
        zynq-zc702.dtb \
        zynq-zc706.dtb \
-       zynq-zed.dtb
+       zynq-zed.dtb \
+       zynq-zybo.dtb
 dtb-$(CONFIG_MACH_ARMADA_370) += \
        armada-370-db.dtb \
        armada-370-mirabox.dtb \

diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
new file mode 100644 (file)
index 0000000..a9a12ce
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -0,0 +1,52 @@
+/*
+ *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+       model = "Zynq ZYBO Development Board";
+       compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x20000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyPS0,115200 earlyprintk";
+       };
+
+};
+
+&clkc {
+       ps-clk-frequency = <50000000>;
+};
+
+&gem0 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy>;
+
+       ethernet_phy: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
+&sdhci0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};