drm/amd/display: Enable pflip interrupt upon pipe enable

[Why]
pflip interrupt would not be enabled promptly if a pipe is disabled
and re-enabled, causing flip_done timeout error during DP
compliance tests

[How]
Enable pflip interrupt upon pipe enablement

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0523be612a48bf878a8e62e9a903c11d5e46ae30..573cf17262da4e116154dc0bb199ef2fc9de4add 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4725,6 +4725,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
        dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
        dc_plane_state->dcc = plane_info.dcc;
        dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
+       dc_plane_state->flip_int_enabled = true;
 
        /*
         * Always set input transfer function, since plane state is refreshed

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4eee3a55fa3018ad0f65bfe50f1e949fbf4de7ac..18ed0d3f247eaec26a0b797603242bbf5e2b9348 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -887,6 +887,7 @@ struct dc_plane_state {
        int layer_index;
 
        union surface_update_flags update_flags;
+       bool flip_int_enabled;
        /* private to DC core */
        struct dc_plane_status status;
        struct dc_context *ctx;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 9e796dfeac2040ea26699b0505c980aaa504c28e..714c71a5fbde3f34e1e16915b5a00583f99fa221 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1257,6 +1257,16 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset)
        REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0);
 }
 
+void hubp1_set_flip_int(struct hubp *hubp)
+{
+       struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+       REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,
+               SURFACE_FLIP_INT_MASK, 1);
+
+       return;
+}
+
 void hubp1_init(struct hubp *hubp)
 {
        //do nothing
@@ -1290,6 +1300,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
        .dmdata_load = NULL,
        .hubp_soft_reset = hubp1_soft_reset,
        .hubp_in_blank = hubp1_in_blank,
+       .hubp_set_flip_int = hubp1_set_flip_int,
 };
 
 /*****************************************/

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index a9a6ed7f4f9932345954fbbdd78dd49760330131..e2f2f6995935f062f09443f73d63dca626badc30 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -74,6 +74,7 @@
        SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
        SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
        SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\
        SRI(HUBPRET_CONTROL, HUBPRET, id),\
        SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
        SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
@@ -183,6 +184,7 @@
        uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
        uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
        uint32_t DCSURF_SURFACE_CONTROL; \
+       uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \
        uint32_t HUBPRET_CONTROL; \
        uint32_t DCN_EXPANSION_MODE; \
        uint32_t DCHUBP_REQ_SIZE_CONFIG; \
@@ -332,6 +334,7 @@
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
@@ -531,6 +534,7 @@
        type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
        type SECONDARY_SURFACE_DCC_EN;\
        type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
+       type SURFACE_FLIP_INT_MASK;\
        type DET_BUF_PLANE1_BASE_ADDRESS;\
        type CROSSBAR_SRC_CB_B;\
        type CROSSBAR_SRC_CR_R;\
@@ -777,4 +781,6 @@ void hubp1_read_state_common(struct hubp *hubp);
 bool hubp1_in_blank(struct hubp *hubp);
 void hubp1_soft_reset(struct hubp *hubp, bool reset);
 
+void hubp1_set_flip_int(struct hubp *hubp);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 89912bb5014f86fe5c57d756b6c209ea8eb02155..9ba5c624770ded1cf08683545bddc1bf50c3661d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2196,6 +2196,13 @@ static void dcn10_enable_plane(
        if (dc->debug.sanity_checks) {
                hws->funcs.verify_allow_pstate_change_high(dc);
        }
+
+       if (!pipe_ctx->top_pipe
+               && pipe_ctx->plane_state
+               && pipe_ctx->plane_state->flip_int_enabled
+               && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
+                       pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
+
 }
 
 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 0df0da2e6a4d05f3c3256913273e41d066bf165f..bec7059f6d5d1579ed84b905f4f2bcd993bfd579 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -1597,6 +1597,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {
        .validate_dml_output = hubp2_validate_dml_output,
        .hubp_in_blank = hubp1_in_blank,
        .hubp_soft_reset = hubp1_soft_reset,
+       .hubp_set_flip_int = hubp1_set_flip_int,
 };
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0726fb435e2a3c175138262f9f3151223aabf77e..5342c309b78c78164b7ad4cfda7e7478e34e450b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1146,6 +1146,12 @@ void dcn20_enable_plane(
                pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
        }
 
+       if (!pipe_ctx->top_pipe
+               && pipe_ctx->plane_state
+               && pipe_ctx->plane_state->flip_int_enabled
+               && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
+                       pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
+
 //     if (dc->debug.sanity_checks) {
 //             dcn10_verify_allow_pstate_change_high(dc);
 //     }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index f9045852728fe5fb0a0b6f8416a0ac188e51a737..b0c9180b808f6cf577bde2704331cad17b173451 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -838,6 +838,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
        .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
        .hubp_init = hubp21_init,
        .validate_dml_output = hubp21_validate_dml_output,
+       .hubp_set_flip_int = hubp1_set_flip_int,
 };
 
 bool hubp21_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index 88ffa9ff1ed15bd5d7e8e7184832fa6c5bd840e6..f246125232482c894f5440c9c6682924577c7f49 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -511,6 +511,7 @@ static struct hubp_funcs dcn30_hubp_funcs = {
        .hubp_init = hubp3_init,
        .hubp_in_blank = hubp1_in_blank,
        .hubp_soft_reset = hubp1_soft_reset,
+       .hubp_set_flip_int = hubp1_set_flip_int,
 };
 
 bool hubp3_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 22f3f643ed1b865ea64af0aadae66a580271bb35..346dcd87dc10651b28bab509b314f21cb89f4c8e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -191,6 +191,8 @@ struct hubp_funcs {
        bool (*hubp_in_blank)(struct hubp *hubp);
        void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
 
+       void (*hubp_set_flip_int)(struct hubp *hubp);
+
 };
 
 #endif