clk: samsung: exynos5422: add missing parent GSCL block clocks

This patch adds clocks, which are required for preserving parent clock
configuration on GSCALLER power domain on/off.

Change-id: I98fd0d78ceb263b0b78960b2704e25b14386316b
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 14bafb39ceb85224d4e2bbe2da22bb028af21b86..db9426800ad50d8d37d2e31498b629d5723bf98d 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -680,8 +680,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                        SRC_TOP5, 20, 1),
        MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
                        mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
-       MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
-                       SRC_TOP5, 28, 1),
+       MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
+                       mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
 
        MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
        MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
@@ -732,8 +732,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                        SRC_TOP12, 20, 1),
        MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
                        mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
-       MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
-                       SRC_TOP12, 28, 1),
+       MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
+                       mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
 
        /* DISP1 Block */
        MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index dde96643e5858d42b1b138018b8034b52e711d06..7699ee9c16c02a6d3f63808a0720aeb073e70370 100644 (file)
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -212,6 +212,8 @@
 #define CLK_MOUT_SW_ACLK300     649
 #define CLK_MOUT_USER_ACLK400_DISP1     650
 #define CLK_MOUT_SW_ACLK400     651
+#define CLK_MOUT_USER_ACLK300_GSCL     652
+#define CLK_MOUT_SW_ACLK300_GSCL       653
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL         768