Convert CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE to Kconfig
authorTom Rini <trini@konsulko.com>
Mon, 1 Aug 2022 01:08:25 +0000 (21:08 -0400)
committerTom Rini <trini@konsulko.com>
Fri, 12 Aug 2022 20:10:49 +0000 (16:10 -0400)
This converts the following to Kconfig:
   CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE

Signed-off-by: Tom Rini <trini@konsulko.com>
configs/pico-imx6_defconfig
configs/warp7_bl33_defconfig
configs/warp7_defconfig
configs/warp_defconfig
drivers/mmc/Kconfig
include/configs/pico-imx6.h
include/configs/warp.h
include/configs/warp7.h

index 086b3ee..45f72d7 100644 (file)
@@ -72,6 +72,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
index a50a1c8..d1c0499 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PINCTRL=y
index 40f9e50..d0b4e74 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PINCTRL=y
index 4c9f705..63f2f21 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
 CONFIG_FSL_USDHC=y
 CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
index c5e1a1b..0dcec8a 100644 (file)
@@ -864,6 +864,10 @@ config FSL_ESDHC_IMX
          This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
          Controller) found on numerous Freescale/NXP SoCs.
 
+config SYS_FSL_ESDHC_HAS_DDR_MODE
+       bool "i.MX eSDHC controller supports DDR mode"
+       depends on FSL_ESDHC_IMX
+
 config FSL_USDHC
        bool "Freescale/NXP i.MX uSDHC controller support"
        depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT
index df4dc4d..dcbcd8d 100644 (file)
@@ -22,7 +22,6 @@
 
 /* MMC Configuration */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC3_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC          (PORT_PTS_UTMI | PORT_PTS_PTW)
index 7cb9743..d2c4391 100644 (file)
@@ -18,7 +18,6 @@
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 
 /* Watchdog */
 
index c00ca4a..7e9b25b 100644 (file)
@@ -15,7 +15,6 @@
 
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 
 #define CONFIG_DFU_ENV_SETTINGS \
        "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \