arm64: dts: renesas: r8a779f0: Add TMU nodes

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 5aff5a2..11c30e3 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -404,6 +404,71 @@
                        #thermal-sensor-cells = <1>;
                };
 
+               tmu0: timer@e61e0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe61e0000 0 0x30>;
+                       interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 713>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 713>;
+                       status = "disabled";
+               };
+
+               tmu1: timer@e6fc0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe6fc0000 0 0x30>;
+                       interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 714>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 714>;
+                       status = "disabled";
+               };
+
+               tmu2: timer@e6fd0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe6fd0000 0 0x30>;
+                       interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 715>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 715>;
+                       status = "disabled";
+               };
+
+               tmu3: timer@e6fe0000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xe6fe0000 0 0x30>;
+                       interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 716>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 716>;
+                       status = "disabled";
+               };
+
+               tmu4: timer@ffc00000 {
+                       compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
+                       reg = <0 0xffc00000 0 0x30>;
+                       interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 717>;
+                       clock-names = "fck";
+                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+                       resets = <&cpg 717>;
+                       status = "disabled";
+               };
+
                i2c0: i2c@e6500000 {
                        compatible = "renesas,i2c-r8a779f0",
                                     "renesas,rcar-gen4-i2c";