drm/msm/dpu1: Add DMA2, DMA3 clock control to enum
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Thu, 13 Jan 2022 14:51:09 +0000 (16:51 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fri, 18 Feb 2022 17:15:10 +0000 (20:15 +0300)
The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though
this driver does actually handle both, if present: add the two in
preparation for adding support for SoCs having them.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220113145111.29984-2-jami.kettunen@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

index 31af04a..736f52c 100644 (file)
@@ -435,6 +435,8 @@ enum dpu_clk_ctrl_type {
        DPU_CLK_CTRL_RGB3,
        DPU_CLK_CTRL_DMA0,
        DPU_CLK_CTRL_DMA1,
+       DPU_CLK_CTRL_DMA2,
+       DPU_CLK_CTRL_DMA3,
        DPU_CLK_CTRL_CURSOR0,
        DPU_CLK_CTRL_CURSOR1,
        DPU_CLK_CTRL_INLINE_ROT0_SSPP,