mips: bmips: dts: add BCM6368 reset controller support

BCM6368 SoCs have a reset controller for certain components.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi
index 449c167..52c19f4 100644 (file)
--- a/arch/mips/boot/dts/brcm/bcm6368.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
@@ -70,6 +70,12 @@
                        mask = <0x1>;
                };
 
+               periph_rst: reset-controller@10000010 {
+                       compatible = "brcm,bcm6345-reset";
+                       reg = <0x10000010 0x4>;
+                       #reset-cells = <1>;
+               };
+
                periph_intc: interrupt-controller@10000020 {
                        compatible = "brcm,bcm6345-l1-intc";
                        reg = <0x10000020 0x10>,

diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h
new file mode 100644 (file)
index 0000000..c81d8eb
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6368-reset.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6368_H
+#define __DT_BINDINGS_RESET_BCM6368_H
+
+#define BCM6368_RST_SPI                0
+#define BCM6368_RST_MPI                3
+#define BCM6368_RST_IPSEC      4
+#define BCM6368_RST_EPHY       6
+#define BCM6368_RST_SAR                7
+#define BCM6368_RST_SWITCH     10
+#define BCM6368_RST_USBD       11
+#define BCM6368_RST_USBH       12
+#define BCM6368_RST_PCM                13
+
+#endif /* __DT_BINDINGS_RESET_BCM6368_H */