clk:starfive:Add PLL2 frequency controller

If enable CONFIG_CLK_STARFIVE_JH7110_PLL, also could read or set PLL1 clock's
rate by reading or setting syscon registers.

Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
index 3e7128c..42e6176 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
@@ -320,7 +320,8 @@ const struct clk_ops *starfive_jh7110_clk_ops(u32 max)
 }
 EXPORT_SYMBOL_GPL(starfive_jh7110_clk_ops);
 
-static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec, void *data)
+static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec,
+                                               void *data)
 {
        struct jh7110_clk_priv *priv = data;
        unsigned int idx = clkspec->args[0];
@@ -330,7 +331,7 @@ static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec, void *data
 
        if (idx < JH7110_CLK_END) {
 #ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
-               if (idx <= JH7110_PLL2_OUT)
+               if ((idx == JH7110_PLL0_OUT) || (idx == JH7110_PLL2_OUT))
                        return &priv->pll_priv[PLL_OF(idx)].hw;
 #endif
                return priv->pll[PLL_OF(idx)];

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
index 27a1399..b2d5970 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
@@ -239,7 +239,13 @@ static int jh7110_clk_pll_determine_rate(struct clk_hw *hw,
        if (ret)
                return ret;
 
-       req->rate = jh7110_pll0_syscon_freq[data->freq_select_idx].freq;
+       if (data->idx == PLL0_INDEX)
+               req->rate = jh7110_pll0_syscon_freq[data->freq_select_idx].freq;
+       else if (data->idx == PLL1_INDEX)
+               req->rate = jh7110_pll1_syscon_freq[data->freq_select_idx].freq;
+       else
+               req->rate = jh7110_pll2_syscon_freq[data->freq_select_idx].freq;
+
        return 0;
 }
 
@@ -249,19 +255,8 @@ static int jh7110_clk_pll_set_rate(struct clk_hw *hw,
 {
        struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
 
-       if (parent_rate != data->refclk_freq) {
-               dev_err(data->dev, "pll%d parent rate is err.\n", data->idx);
-               goto rate_err;
-       }
-       if (rate != jh7110_pll0_syscon_freq[data->freq_select_idx].freq) {
-               dev_err(data->dev, "pll%d rate is err.\n", data->idx);
-               goto rate_err;
-       }
-
        return pll_set_freq_syscon(data);
 
-rate_err:
-       return -EINVAL;
 }
 
 #ifdef CONFIG_DEBUG_FS
@@ -422,6 +417,11 @@ int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev,
                        .num_parents = 1,
                        .flags = 0,
                };
+
+               /* pll1 use default freq and does not be changed */
+               if (idx == PLL1_INDEX)
+                       continue;
+
                data = &pll_priv[idx];
                data->dev = &pdev->dev;
                data->sys_syscon_regmap = pll_syscon_regmap;
@@ -439,7 +439,8 @@ int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev,
                        return ret;
        }
 
-       dev_info(&pdev->dev, "%d pll clock be set done\n", PLL_INDEX_MAX);
+       dev_info(&pdev->dev, "PLL0 and PLL2 clock be set done\n");
+
        return 0;
 
 pll_init_failed:

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
index 3f1011b..71c6f82 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-pll.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
@@ -8,17 +8,13 @@
 #ifndef _CLK_STARFIVE_JH7110_PLL_H_
 #define _CLK_STARFIVE_JH7110_PLL_H_
 
-#define OSC_DEFAULT_FREQ       24000000
+#define PLL2_DEFAULT_FREQ      PLL2_FREQ_1188_VALUE
+
 #define PLL0_INDEX             0
-#define PLL0_DEFAULT_FREQ      1250000000
 #define PLL1_INDEX             1
-#define PLL1_DEFAULT_FREQ      1066000000
 #define PLL2_INDEX             2
-#define PLL2_DEFAULT_FREQ      1228800000
-/* If only pll0, PLL_INDEX_MAX should be 1.
- * If want to control pll1 and pll2 ,then should be 3.
- */
-#define PLL_INDEX_MAX  1
+
+#define PLL_INDEX_MAX  3
 
 #define PLL0_DACPD_SHIFT       24
 #define PLL0_DACPD_MASK                0x1000000
@@ -152,11 +148,13 @@ enum starfive_pll1_freq {
 };
 
 enum starfive_pll2_freq_value {
+       PLL2_FREQ_1188_VALUE = 1188000000,
        PLL2_FREQ_12288_VALUE = 1228800000,
 };
 
 enum starfive_pll2_freq {
-       PLL2_FREQ_12288 = 0,
+       PLL2_FREQ_1188 = 0,
+       PLL2_FREQ_12288,
 };
 
 static const struct starfive_pll_syscon_value
@@ -265,6 +263,14 @@ static const struct starfive_pll_syscon_value
 
 static const struct starfive_pll_syscon_value
        jh7110_pll2_syscon_freq[] = {
+       [PLL2_FREQ_1188] = {
+               .freq = PLL2_FREQ_1188_VALUE,
+               .prediv = 2,
+               .fbdiv = 99,
+               .postdiv1 = 1,
+               .dacpd = 1,
+               .dsmpd = 1,
+       },
        [PLL2_FREQ_12288] = {
                .freq = PLL2_FREQ_12288_VALUE,
                .prediv = 5,

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index aaeec72..73051bb 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -493,11 +493,13 @@ int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
        if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]))
                return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]);
 
+#ifndef CONFIG_CLK_STARFIVE_JH7110_PLL
        priv->pll[PLL_OF(JH7110_PLL2_OUT)] =
                        clk_hw_register_fixed_rate(priv->dev,
                        "pll2_out", "osc", 0, 1228800000);
        if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]))
                return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]);
+#endif
 
        priv->pll[PLL_OF(JH7110_AON_APB)] =
                        devm_clk_hw_register_fixed_factor(priv->dev,
@@ -800,7 +802,7 @@ int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
                        if (pidx < JH7110_CLK_SYS_REG_END)
                                parents[i].hw = &priv->reg[pidx].hw;
 #ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
-                       else if (pidx == JH7110_PLL0_OUT)
+                       else if ((pidx == JH7110_PLL0_OUT) || (pidx == JH7110_PLL2_OUT))
                                parents[i].hw = &priv->pll_priv[PLL_OF(pidx)].hw;
 #endif
                        else if ((pidx < JH7110_CLK_SYS_END) &&