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drm/amdgpu: Fix GRBM programming sequence
author
Lijo Lazar
<lijo.lazar@amd.com>
Wed, 6 Jul 2022 08:20:45 +0000
(13:50 +0530)
committer
Alex Deucher
<alexander.deucher@amd.com>
Fri, 9 Jun 2023 13:45:54 +0000
(09:45 -0400)
It needs to be done only for XCC instances in non-AID0. Use the physical
instance to determine non-AID0 XCC instances.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
patch
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index
e9c12b4
..
43126f7
100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@
-186,11
+186,14
@@
static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
{
- int i, num_xcc;
+ int i, num_xcc
, dev_inst
;
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
- for (i = 2; i < num_xcc; i++)
- WREG32_SOC15(GC, GET_INST(GC, i), regGRBM_MCM_ADDR, 0x4);
+ for (i = 0; i < num_xcc; i++) {
+ dev_inst = GET_INST(GC, i);
+ if (dev_inst >= 2)
+ WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4);
+ }
}
static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,