clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
+
return 0;
}
{
struct stfcamss *stfcamss = csi_dev->stfcamss;
+ reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
+
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
clk_set_rate(stfcamss->sys_clk[STFCLK_M31DPHY_TXCLKESC_LAN0].clk,
20480000);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_M31DPHY_HW].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_M31DPHY_B09_ALWAYS_ON].rstc);
+
count++;
} else {
if (count == 0)
goto exit;
-
+ if (count == 1) {
+ reset_control_assert(stfcamss->sys_rst[STFRST_M31DPHY_HW].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_M31DPHY_B09_ALWAYS_ON].rstc);
+ }
count--;
}
exit:
struct stfcamss *stfcamss = isp_dev->stfcamss;
clk_prepare_enable(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_WRAPPER_C].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_WRAPPER_P].rstc);
return 0;
}
{
struct stfcamss *stfcamss = isp_dev->stfcamss;
+ //reset STFRST_WRAPPER_C would cause error
+ //reset_control_assert(stfcamss->sys_rst[STFRST_WRAPPER_C].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_WRAPPER_P].rstc);
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk);
return 0;
clk_prepare_enable(stfcamss->sys_clk[STFCLK_ISPCORE_2X].clk);
clk_prepare_enable(stfcamss->sys_clk[STFCLK_ISP_AXI].clk);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_ISP_TOP_N].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rstc);
return 0;
}
{
struct stfcamss *stfcamss = vin_dev->stfcamss;
+ reset_control_assert(stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_ISP_TOP_N].rstc);
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_ISP_AXI].clk);
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_ISPCORE_2X].clk);
static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
{
struct stfcamss *stfcamss = vin_dev->stfcamss;
- int ret;
clk_prepare_enable(stfcamss->sys_clk[STFCLK_PCLK].clk);
clk_set_rate(stfcamss->sys_clk[STFCLK_APB_FUNC].clk, 51200000);
clk_set_rate(stfcamss->sys_clk[STFCLK_SYS_CLK].clk, 307200000);
- ret = reset_control_deassert(stfcamss->resets);
- if (ret)
- dev_err(stfcamss->dev, "deassert stfcamss error.\n");
+ reset_control_deassert(stfcamss->sys_rst[STFRST_PCLK].rstc);
+ reset_control_deassert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
- return ret;
+ return 0;
}
static int stf_vin_clk_disable(struct stf_vin2_dev *vin_dev)
{
struct stfcamss *stfcamss = vin_dev->stfcamss;
- int ret;
- ret = reset_control_assert(stfcamss->resets);
- if (ret)
- dev_err(stfcamss->dev, "assert stfcamss error.\n");
+ reset_control_assert(stfcamss->sys_rst[STFRST_PCLK].rstc);
+ reset_control_assert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PCLK].clk);
- return ret;
+ return 0;
}
static int stf_vin_config_set(struct stf_vin2_dev *vin_dev)
static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
{
+ struct stfcamss *stfcamss = vin_dev->stfcamss;
struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
//make the axiwr alway on
- if (on)
+ if (on) {
+ reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
reg_set(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);
+ }
return 0;
}
{ .id = "clk_noc_bus_clk_isp_axi" },
};
+static struct reset_control_bulk_data stfcamss_resets[] = {
+ { .id = "rst_wrapper_p" },
+ { .id = "rst_wrapper_c" },
+ { .id = "rst_pclk" },
+ { .id = "rst_sys_clk" },
+ { .id = "rst_axird" },
+ { .id = "rst_axiwr" },
+ { .id = "rst_pixel_clk_if0" },
+ { .id = "rst_pixel_clk_if1" },
+ { .id = "rst_pixel_clk_if2" },
+ { .id = "rst_pixel_clk_if3" },
+ { .id = "rst_m31dphy_hw" },
+ { .id = "rst_m31dphy_b09_always_on" },
+ { .id = "rst_isp_top_n" },
+ { .id = "rst_isp_top_axi" },
+};
+
int stfcamss_get_mem_res(struct platform_device *pdev, struct stf_vin_dev *vin)
{
struct device *dev = &pdev->dev;
return ret;
}
- stfcamss->resets = devm_reset_control_array_get_shared(dev);
- if (IS_ERR(stfcamss->resets)) {
- st_err(ST_CAMSS, "Failed to get stfcamss reset controls\n");
- return PTR_ERR(stfcamss->resets);
+ stfcamss->nrsts = ARRAY_SIZE(stfcamss_resets);
+ stfcamss->sys_rst = stfcamss_resets;
+
+ ret = devm_reset_control_bulk_get_exclusive(dev, stfcamss->nrsts,
+ stfcamss->sys_rst);
+ if (ret) {
+ st_err(ST_CAMSS, "Failed to get reset controls\n");
+ return ret;
}
ret = of_parse_phandle_with_fixed_args(dev->of_node,
STFCLK_NUM
};
+enum stf_rst_num {
+ STFRST_WRAPPER_P = 0,
+ STFRST_WRAPPER_C,
+ STFRST_PCLK,
+ STFRST_SYS_CLK,
+ STFRST_AXIRD,
+ STFRST_AXIWR,
+ STFRST_PIXEL_CLK_IF0,
+ STFRST_PIXEL_CLK_IF1,
+ STFRST_PIXEL_CLK_IF2,
+ STFRST_PIXEL_CLK_IF3,
+ STFRST_M31DPHY_HW,
+ STFRST_M31DPHY_B09_ALWAYS_ON,
+ STFRST_ISP_TOP_N,
+ STFRST_ISP_TOP_AXI,
+ STFRST_NUM
+};
+
struct stfcamss {
struct stf_vin_dev *vin; // stfcamss phy res
struct v4l2_device v4l2_dev;
struct v4l2_async_notifier notifier;
struct clk_bulk_data *sys_clk;
int nclks;
- struct reset_control *resets;
+ struct reset_control_bulk_data *sys_rst;
+ int nrsts;
struct regmap *stf_aon_syscon;
uint32_t aon_gp_reg;
#ifdef CONFIG_DEBUG_FS