PD#161475: ddr: fix overflow when ddr freq is high
Caculate of ddr freq will overflow if ddr freq is
over 1.5GHz, This commit fixed it.
Change-Id: Idc07b1022b52e3ec5c227c15afff1aaf21575ed7
Signed-off-by: tao zeng <tao.zeng@amlogic.com>
m = val & 0x1ff;
n = ((val >> 10) & 0x1f);
od1 = (((val >> 19) & 0x1)) == 1 ? 2 : 1;
+ freq = DEFAULT_XTAL_FREQ / 1000; /* avoid overflow */
if (n)
- freq = (((DEFAULT_XTAL_FREQ * m) / n) >> od1) / od_div;
+ freq = ((((freq * m) / n) >> od1) / od_div) * 1000;
return freq;
}
(db->cpu_type < MESON_CPU_MAJOR_ID_GXL)) {
od1 = (val >> 14) & 0x03;
}
- freq = (DEFAULT_XTAL_FREQ * m / (n * (1 + od))) >> od1;
+ freq = DEFAULT_XTAL_FREQ / 1000; /* avoid overflow */
+ freq = ((freq * m / (n * (1 + od))) >> od1) * 1000;
return freq;
}
m = (val >> 4) & 0x1ff;
n = (val >> 16) & 0x1f;
od1 = (val >> 0) & 0x03;
- freq = (DEFAULT_XTAL_FREQ * m / (n * (1 + od))) >> od1;
+ freq = DEFAULT_XTAL_FREQ / 1000; /* avoid overflow */
+ freq = ((freq * m / (n * (1 + od))) >> od1) * 1000;
return freq;
}
#define DEFAULT_CLK_CNT 12000000
-#define DEFAULT_XTAL_FREQ 24000000
+#define DEFAULT_XTAL_FREQ 24000000UL
#define DMC_QOS_IRQ (1 << 30)
#define MAX_CHANNEL 4