projects
/
platform
/
kernel
/
u-boot.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
3fb4ef7
)
clk: zynqmp: Add set_rate support for gem rx and tsu clks
author
Ashok Reddy Soma
<ashok.reddy.soma@amd.com>
Wed, 19 Jul 2023 08:49:12 +0000
(
02:49
-0600)
committer
Michal Simek
<michal.simek@amd.com>
Fri, 21 Jul 2023 07:00:39 +0000
(09:00 +0200)
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link:
https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers/clk/clk_zynqmp.c
patch
|
blob
|
history
diff --git
a/drivers/clk/clk_zynqmp.c
b/drivers/clk/clk_zynqmp.c
index
8320d49
..
53327cf
100644
(file)
--- a/
drivers/clk/clk_zynqmp.c
+++ b/
drivers/clk/clk_zynqmp.c
@@
-719,6
+719,8
@@
static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
+ case gem0_rx ... gem3_rx:
+ case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,