arm64/sysreg: Generate definitions for SCTLR_EL1

Automatically generate register definitions for SCTLR_EL1. No functional
change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220503170233.507788-13-broonie@kernel.org
[catalin.marinas@arm.com: fix the SCTLR_EL1 encoding]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c61bda1db2c8bb06a7465b698c7277ff93e979fb..a6b8b0deadfbdd6c1e0ff38767de09002305ec1a 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -203,7 +203,6 @@
 #define SYS_ID_AA64MMFR1_EL1           sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1           sys_reg(3, 0, 0, 7, 2)
 
-#define SYS_SCTLR_EL1                  sys_reg(3, 0, 1, 0, 0)
 #define SYS_ACTLR_EL1                  sys_reg(3, 0, 1, 0, 1)
 #define SYS_CPACR_EL1                  sys_reg(3, 0, 1, 0, 2)
 #define SYS_RGSR_EL1                   sys_reg(3, 0, 1, 0, 5)
@@ -677,43 +676,6 @@
        (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
 
 /* SCTLR_EL1 specific flags. */
-#define SCTLR_EL1_EPAN         (BIT(57))
-#define SCTLR_EL1_ATA0         (BIT(42))
-
-#define SCTLR_EL1_TCF_SHIFT    40
-#define SCTLR_EL1_TCF_NONE     (UL(0x0))
-#define SCTLR_EL1_TCF_SYNC     (UL(0x1))
-#define SCTLR_EL1_TCF_ASYNC    (UL(0x2))
-#define SCTLR_EL1_TCF_ASYMM    (UL(0x3))
-#define SCTLR_EL1_TCF_MASK     (UL(0x3) << SCTLR_EL1_TCF_SHIFT)
-
-#define SCTLR_EL1_TCF0_SHIFT   38
-#define SCTLR_EL1_TCF0_NONE    (UL(0x0))
-#define SCTLR_EL1_TCF0_SYNC    (UL(0x1))
-#define SCTLR_EL1_TCF0_ASYNC   (UL(0x2))
-#define SCTLR_EL1_TCF0_ASYMM   (UL(0x3))
-#define SCTLR_EL1_TCF0_MASK    (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
-
-#define SCTLR_EL1_BT1          (BIT(36))
-#define SCTLR_EL1_BT0          (BIT(35))
-#define SCTLR_EL1_LSMAOE       (BIT(29))
-#define SCTLR_EL1_nTLSMD       (BIT(28))
-#define SCTLR_EL1_UCI          (BIT(26))
-#define SCTLR_EL1_E0E          (BIT(24))
-#define SCTLR_EL1_SPAN         (BIT(23))
-#define SCTLR_EL1_EIS          (BIT(22))
-#define SCTLR_EL1_TSCXT                (BIT(20))
-#define SCTLR_EL1_nTWE         (BIT(18))
-#define SCTLR_EL1_nTWI         (BIT(16))
-#define SCTLR_EL1_UCT          (BIT(15))
-#define SCTLR_EL1_DZE          (BIT(14))
-#define SCTLR_EL1_EOS          (BIT(11))
-#define SCTLR_EL1_UMA          (BIT(9))
-#define SCTLR_EL1_SED          (BIT(8))
-#define SCTLR_EL1_ITD          (BIT(7))
-#define SCTLR_EL1_CP15BEN      (BIT(5))
-#define SCTLR_EL1_SA0          (BIT(4))
-
 #ifdef CONFIG_CPU_BIG_ENDIAN
 #define ENDIAN_SET_EL1         (SCTLR_EL1_E0E | SCTLR_ELx_EE)
 #else

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index e77354847a6413ecede7a53aff71bb3b03a72f18..c5619629bf9c0ba844e6c8170a040605838d8191 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -114,6 +114,77 @@ EndEnum
 Res0   3:0
 EndSysreg
 
+Sysreg SCTLR_EL1       3       0       1       0       0
+Field  63      TIDCP
+Field  62      SPINMASK
+Field  61      NMI
+Field  60      EnTP2
+Res0   59:58
+Field  57      EPAN
+Field  56      EnALS
+Field  55      EnAS0
+Field  54      EnASR
+Field  53      TME
+Field  52      TME0
+Field  51      TMT
+Field  50      TMT0
+Field  49:46   TWEDEL
+Field  45      TWEDEn
+Field  44      DSSBS
+Field  43      ATA
+Field  42      ATA0
+Enum   41:40   TCF
+       0b00    NONE
+       0b01    SYNC
+       0b10    ASYNC
+       0b11    ASYMM
+EndEnum
+Enum   39:38   TCF0
+       0b00    NONE
+       0b01    SYNC
+       0b10    ASYNC
+       0b11    ASYMM
+EndEnum
+Field  37      ITFSB
+Field  36      BT1
+Field  35      BT0
+Res0   34
+Field  33      MSCEn
+Field  32      CMOW
+Field  31      EnIA
+Field  30      EnIB
+Field  29      LSMAOE
+Field  28      nTLSMD
+Field  27      EnDA
+Field  26      UCI
+Field  25      EE
+Field  24      E0E
+Field  23      SPAN
+Field  22      EIS
+Field  21      IESB
+Field  20      TSCXT
+Field  19      WXN
+Field  18      nTWE
+Res0   17
+Field  16      nTWI
+Field  15      UCT
+Field  14      DZE
+Field  13      EnDB
+Field  12      I
+Field  11      EOS
+Field  10      EnRCTX
+Field  9       UMA
+Field  8       SED
+Field  7       ITD
+Field  6       nAA
+Field  5       CP15BEN
+Field  4       SA0
+Field  3       SA
+Field  2       C
+Field  1       A
+Field  0       M
+EndSysreg
+
 SysregFields TTBRx_EL1
 Field  63:48   ASID
 Field  47:1    BADDR