the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-
/* Instruction scheduling pass.
This pass implements list scheduling within basic blocks. It is
/* nr_inter/spec counts interblock/speculative motion for the function. */
static int nr_inter, nr_spec;
-
/* Debugging file. All printouts are sent to dump, which is always set,
either to stderr, or to the dump listing file (-dRS). */
static FILE *dump = 0;
branches for typical C code. So we can make a guess that the average
basic block is approximately 5 instructions long; we will choose 100X
the average size as a very large basic block.
-
+
Each insn has an associated bitmap for its dependencies. Each bitmap
has enough entries to represent a dependency on any other insn in the
insn chain. */
it represents forward dependancies. */
rtx depend;
- /* The line number note in effect for each insn. For line number
+ /* The line number note in effect for each insn. For line number
notes, this indicates whether the note may be reused. */
rtx line_note;
static int priority PARAMS ((rtx));
static void free_pending_lists PARAMS ((void));
static void add_insn_mem_dependence PARAMS ((struct deps *, rtx *, rtx *, rtx,
- rtx));
+ rtx));
static void flush_pending_lists PARAMS ((struct deps *, rtx, int));
static void sched_analyze_1 PARAMS ((struct deps *, rtx, rtx));
static void sched_analyze_2 PARAMS ((struct deps *, rtx, rtx));
/* Control flow graph edges are kept in circular lists. */
typedef struct
- {
- int from_block;
- int to_block;
- int next_in;
- int next_out;
- }
+{
+ int from_block;
+ int to_block;
+ int next_in;
+ int next_out;
+}
haifa_edge;
static haifa_edge *edge_table;
#define IN_EDGES(block) (in_edges[block])
#define OUT_EDGES(block) (out_edges[block])
-
-
static int is_cfg_nonregular PARAMS ((void));
static int build_control_flow PARAMS ((struct edge_list *));
static void new_edge PARAMS ((int, int));
-
/* A region is the main entity for interblock scheduling: insns
are allowed to move between blocks in the same region, along
control flow graph edges, in the 'up' direction. */
typedef struct
- {
- int rgn_nr_blocks; /* Number of blocks in region. */
- int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */
- }
+{
+ int rgn_nr_blocks; /* Number of blocks in region. */
+ int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */
+}
region;
/* Number of regions in the procedure. */
/* The mapping from bb to block. */
#define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)])
-
/* Bit vectors and bitset operations are needed for computations on
the control flow graph. */
typedef unsigned HOST_WIDE_INT *bitset;
typedef struct
- {
- int *first_member; /* Pointer to the list start in bitlst_table. */
- int nr_members; /* The number of members of the bit list. */
- }
+{
+ int *first_member; /* Pointer to the list start in bitlst_table. */
+ int nr_members; /* The number of members of the bit list. */
+}
bitlst;
static int bitlst_table_last;
about such sources: are they valid? Speculative? Etc. */
typedef bitlst bblst;
typedef struct
- {
- char is_valid;
- char is_speculative;
- int src_prob;
- bblst split_bbs;
- bblst update_bbs;
- }
+{
+ char is_valid;
+ char is_speculative;
+ int src_prob;
+ bblst split_bbs;
+ bblst update_bbs;
+}
candidate;
static candidate *candidate_table;
void debug_candidate PARAMS ((int));
void debug_candidates PARAMS ((int));
-
/* Bit-set of bbs, where bit 'i' stands for bb 'i'. */
typedef bitset bbset;
static void get_block_head_tail PARAMS ((int, rtx *, rtx *));
static void get_bb_head_tail PARAMS ((int, rtx *, rtx *));
-static int queue_to_ready PARAMS ((rtx [], int));
+static int queue_to_ready PARAMS ((rtx[], int));
static void debug_ready_list PARAMS ((rtx[], int));
static void init_target_units PARAMS ((void));
such dependency is useless and can be ignored. */
if (GET_CODE (elem) == NOTE)
return;
-
+
/* If elem is part of a sequence that must be scheduled together, then
make the dependence point to the last insn of the sequence.
When HAVE_cc0, it is possible for NOTEs to exist between users and
#ifdef INSN_SCHEDULING
/* If we are adding a true dependency to INSN's LOG_LINKs, then
note that in the bitmap cache of true dependency information. */
- if ((int)dep_type == 0 && true_dependency_cache)
+ if ((int) dep_type == 0 && true_dependency_cache)
SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem));
#endif
return;
#ifdef INSN_SCHEDULING
/* If we are adding a true dependency to INSN's LOG_LINKs, then
note that in the bitmap cache of true dependency information. */
- if ((int)dep_type == 0 && true_dependency_cache)
+ if ((int) dep_type == 0 && true_dependency_cache)
SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem));
#endif
}
return unreachable;
}
-
/* Record an edge in the control flow graph from SOURCE to TARGET.
In theory, this is redundant with the s_succs computed above, but
}
}
-
/* BITSET macros for operations on the control flow graph. */
/* Compute bitwise union of two bitsets. */
~(1 << (index%HOST_BITS_PER_WIDE_INT)); \
}
-
/* Check if the index'th bit in bitset set is on. */
static char
1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0;
}
-
/* Translate a bit-set SET to a list BL of the bit-set members. */
static void
}
-
/* Functions for the construction of regions. */
/* Print the regions, for debugging purposes. Callable from debugger. */
}
}
-
/* Build a single block region for each basic block in the function.
This allows for using the same code for interblock and basic block
scheduling. */
nr_regions = n_basic_blocks;
}
-
/* Update number of blocks and the estimate for number of insns
in the region. Return 1 if the region is "too large" for interblock
scheduling (compile time considerations), otherwise return 0. */
return 0;
}
-
/* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk]
is still an inner loop. Put in max_hdr[blk] the header of the most inner
loop containing blk. */
} \
}
-
/* Find regions for interblock scheduling.
A region for scheduling can be:
* A basic block not contained in any other region.
-
?!? In theory we could build other regions based on extended basic
blocks or reverse extended basic blocks. Is it worth the trouble?
* block_to_bb
* containing region
-
We use dominator relationships to avoid making regions out of non-reducible
loops.
/* Note if a block is an natural inner loop header. */
sbitmap inner;
- /* Note if a block is in the block queue. */
+ /* Note if a block is in the block queue. */
sbitmap in_queue;
- /* Note if a block is in the block queue. */
+ /* Note if a block is in the block queue. */
sbitmap in_stack;
int num_edges = NUM_EDGES (edge_list);
out edge. However, if the node has no out edge then we will
not set dfs_nr for that node. This can confuse the scheduler
into thinking that we have unreachable blocks, which in turn
- disables cross block scheduling.
+ disables cross block scheduling.
So, if we have a node with no out edges, go ahead and mark it
as reachable now. */
If there exists a block that is not dominated by the loop
header, then the block is reachable from outside the loop
and thus the loop is not a natural loop. */
- for (j = 0; j < n_basic_blocks; j++)
+ for (j = 0; j < n_basic_blocks; j++)
{
/* First identify blocks in the loop, except for the loop
entry block. */
/* Estimate # insns, and count # blocks in the region. */
num_bbs = 1;
- num_insns = (INSN_LUID (BLOCK_END (i))
+ num_insns = (INSN_LUID (BLOCK_END (i))
- INSN_LUID (BLOCK_HEAD (i)));
-
/* Find all loop latches (blocks with back edges to the loop
header) or all the leaf blocks in the cfg has no loops.
break;
}
}
-
}
}
c a,d
d b
-
The algorithm in the DFS traversal may not mark B & D as part
of the loop (ie they will not have max_hdr set to A).
We do not do this because I'm not sure that the actual
scheduling code will properly handle this case. ?!? */
-
+
while (head < tail && !too_large_failure)
{
edge e;
free (in_stack);
}
-
/* Functions for regions scheduling information. */
/* Compute dominators, probability, and potential-split-edges of bb.
BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size);
if (sched_verbose >= 2)
- fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb]));
-} /* compute_dom_prob_ps */
+ fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb),
+ (int) (100.0 * prob[bb]));
+}
/* Functions for target info. */
free (src);
}
-
/* Find the valid candidate-source-blocks for the target block TRG, compute
their probability, and check if they are speculative or not.
For speculative sources, compute their update-blocks and split-blocks. */
sp->src_prob = 0;
}
}
-} /* compute_trg_info */
-
+}
/* Print candidates info, for debugging purposes. Callable from debugger. */
}
}
-
/* Print candidates info, for debugging purposes. Callable from debugger. */
void
debug_candidate (i);
}
-
/* Functions for speculative scheduing. */
/* Return 0 if x is a set of a register alive in the beginning of one
return 1;
}
-
/* If x is a set of a register R, mark that R is alive in the beginning
of every update-block of src. */
}
}
-
/* Return 1 if insn can be speculatively moved from block src to trg,
otherwise return 0. Called before first insertion of insn to
ready-list or before the scheduling. */
return 1;
}
-
/* Update the live registers info after insn was moved speculatively from
block src to trg. */
}
return insn_class;
}
-} /* may_trap_exp */
-
+}
/* Classifies insn for the purpose of verifying that it can be
moved speculatively, by examining it's patterns, returning:
/* Test if it is a load. */
tmp_class =
WORST_CLASS (tmp_class,
- may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0));
+ may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0));
break;
case COND_EXEC:
case TRAP_IF:
}
return insn_class;
-
-} /* haifa_classify_insn */
+}
/* Return 1 if load_insn is prisky (i.e. if load_insn is fed by
a load moved speculatively, or if load_insn is protected by
return 1;
return 0;
-} /* is_prisky */
+}
/* Insn is a candidate to be moved speculatively from bb_src to bb_trg.
Return 1 if insn is exception-free (and the motion is valid)
}
return flag_schedule_speculative_load_dangerous;
-} /* is_exception_free */
-
+}
/* Process an insn's memory dependencies. There are four kinds of
dependencies:
return 0;
}
-
/* Compute the function units used by INSN. This caches the value
returned by function_units_used. A function unit is encoded as the
unit number if the value is non-negative and the compliment of a
return this_priority;
}
\f
-
/* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
them to the unused_*_list variables, so that they can be reused. */
}
while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
- || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
+ || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
{
if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
{
if (code == SET)
{
free_INSN_LIST_list (&deps->reg_last_uses[r]);
- for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1))
+ for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1))
add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
- SET_REGNO_REG_SET (reg_pending_sets, r);
+ SET_REGNO_REG_SET (reg_pending_sets, r);
}
else
SET_REGNO_REG_SET (reg_pending_clobbers, r);
while (pending)
{
if (true_dependence (XEXP (pending_mem, 0), VOIDmode,
- x, rtx_varies_p))
+ x, rtx_varies_p))
add_dependence (insn, XEXP (pending, 0), 0);
pending = XEXP (pending, 1);
/* If a post-call group is still open, see if it should remain so.
This insn must be a simple move of a hard reg to a pseudo or
- vice-versa.
+ vice-versa.
We must avoid moving these insns for correctness on
SMALL_REGISTER_CLASS machines, and for special registers like
- PIC_OFFSET_TABLE_REGNUM. For simplicity, extend this to all
+ PIC_OFFSET_TABLE_REGNUM. For simplicity, extend this to all
hard regs for all targets. */
if (deps->in_post_call_group_p)
free_INSN_LIST_list (&deps->last_function_call);
deps->last_function_call = alloc_INSN_LIST (insn, NULL_RTX);
- /* Before reload, begin a post-call group, so as to keep the
+ /* Before reload, begin a post-call group, so as to keep the
lifetimes of hard registers correct. */
if (! reload_completed)
deps->in_post_call_group_p = 1;
}
- /* See comments on reemit_notes as to why we do this.
+ /* See comments on reemit_notes as to why we do this.
??? Actually, the reemit_notes just say what is done, not why. */
else if (GET_CODE (insn) == NOTE
const PTR x;
const PTR y;
{
- rtx tmp = *(const rtx *)y;
- rtx tmp2 = *(const rtx *)x;
+ rtx tmp = *(const rtx *) y;
+ rtx tmp2 = *(const rtx *) x;
rtx link;
int tmp_class, tmp2_class, depend_count1, depend_count2;
int val, priority_val, spec_val, prob_val, weight_val;
-
/* Prefer insn with higher priority. */
priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
if (priority_val)
return val;
}
- /* Prefer the insn which has more later insns that depend on it.
+ /* Prefer the insn which has more later insns that depend on it.
This gives the scheduler more freedom when scheduling later
instructions at the expense of added register pressure. */
depend_count1 = 0;
val = depend_count2 - depend_count1;
if (val)
return val;
-
+
/* If insns are equally good, sort by INSN_LUID (original insn order),
so that we make the sort stable. This minimizes instruction movement,
thus minimizing sched's effect on debugging and cross-jumping. */
{
/* ??? There used to be code here to try and estimate how an insn
affected register lifetimes, but it did it by looking at REG_DEAD
- notes, which we removed in schedule_region. Nor did it try to
+ notes, which we removed in schedule_region. Nor did it try to
take into account register pressure or anything useful like that.
Revisit when we have a machine model to work with and not before. */
if (sched_verbose >= 2)
{
- fprintf (dump, ";;\t\tdependences resolved: insn %d ",
+ fprintf (dump, ";;\t\tdependences resolved: insn %d ",
INSN_UID (next));
if (current_nr_blocks > 1 && INSN_BB (next) != target_bb)
}
}
- /* Annotate the instruction with issue information -- TImode
+ /* Annotate the instruction with issue information -- TImode
indicates that the instruction is expected not to be able
to issue on the same cycle as the previous insn. A machine
may use this information to decide how the instruction should
LINE_NOTE (insn) = line;
}
-
/* After bb was scheduled, insert line notes into the insns list. */
static void
static void
find_insn_reg_weight (b)
- int b;
+ int b;
{
rtx insn, next_tail, head, tail;
q_size -= 1;
if (sched_verbose >= 2)
- fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
+ fprintf (dump, ";;\t\tQ-->Ready: insn %d: ",
+ INSN_UID (insn));
if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
char tmp[BUF_LEN];
const char *st[4];
char *cur = buf;
- const char *fun = (char *)0;
+ const char *fun = (char *) 0;
const char *sep;
rtx op[4];
int i;
for (i = 0; i < 4; i++)
{
- st[i] = (char *)0;
+ st[i] = (char *) 0;
op[i] = NULL_RTX;
}
cur = safe_concat (buf, cur, t);
break;
case CONST_DOUBLE:
- sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
+ sprintf (t, "<0x%lx,0x%lx>", (long) XWINT (x, 2), (long) XWINT (x, 3));
cur = safe_concat (buf, cur, t);
break;
case CONST_STRING:
case REG:
if (REGNO (x) < FIRST_PSEUDO_REGISTER)
{
- int c = reg_names[ REGNO (x) ][0];
+ int c = reg_names[REGNO (x)][0];
if (c >= '0' && c <= '9')
cur = safe_concat (buf, cur, "%");
- cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]);
+ cur = safe_concat (buf, cur, reg_names[REGNO (x)]);
}
else
{
/* Prepare current target block info. */
if (current_nr_blocks > 1)
{
- candidate_table = (candidate *) xmalloc (current_nr_blocks
+ candidate_table = (candidate *) xmalloc (current_nr_blocks
* sizeof (candidate));
bblst_last = 0;
if (sched_verbose >= 5)
debug_dependencies ();
-
/* Initialize ready list with all 'ready' insns in target block.
Count number of insns in the target block being scheduled. */
n_ready = 0;
{
rtx next;
- /* Note that we havn't squirrled away the notes for
+ /* Note that we havn't squirrled away the notes for
blocks other than the current. So if this is a
speculative insn, NEXT might otherwise be a note. */
next = next_nonnote_insn (insn);
/* Sort the ready list based on priority. */
SCHED_SORT (ready, n_ready);
- /* Allow the target to reorder the list, typically for
+ /* Allow the target to reorder the list, typically for
better instruction bundling. */
#ifdef MD_SCHED_REORDER
MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var,
nr_inter++;
/* Find the beginning of the scheduling group. */
- /* ??? Ought to update basic block here, but later bits of
- schedule_block assumes the original insn block is
+ /* ??? Ought to update basic block here, but later bits of
+ schedule_block assumes the original insn block is
still intact. */
temp = insn;
free (ready);
return (sched_n_insns);
-} /* schedule_block () */
+}
\f
-
/* Print the bit-set of registers, S, callable from debugger. */
extern void
/* last_pending_memory_flush is inherited by bb_succ. */
for (u = tmp_deps->last_pending_memory_flush; u; u = XEXP (u, 1))
{
- if (find_insn_list (XEXP (u, 0),
+ if (find_insn_list (XEXP (u, 0),
succ_deps->last_pending_memory_flush))
continue;
/* Free up the INSN_LISTs.
- Note this loop is executed max_reg * nr_regions times. It's first
+ Note this loop is executed max_reg * nr_regions times. It's first
implementation accounted for over 90% of the calls to free_INSN_LIST_list.
- The list was empty for the vast majority of those calls. On the PA, not
+ The list was empty for the vast majority of those calls. On the PA, not
calling free_INSN_LIST_list in those cases improves -O2 compile times by
3-5% on average. */
for (i = 0; i < max_reg; ++i)
edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1;
edgeset_bitsize = rgn_nr_edges;
pot_split = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset));
- ancestor_edges
+ ancestor_edges
= (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset));
for (i = 0; i < current_nr_blocks; i++)
{
if (insn == BLOCK_END (b))
break;
}
-
+
/* ?!? We could save some memory by computing a per-region luid mapping
which could reduce both the number of vectors in the cache and the size
of each vector. Instead we just avoid the cache entirely unless the
{
sbitmap_zero (blocks);
for (b = RGN_NR_BLOCKS (rgn) - 1; b >= 0; --b)
- SET_BIT (blocks, rgn_bb_table [RGN_BLOCKS (rgn) + b]);
+ SET_BIT (blocks, rgn_bb_table[RGN_BLOCKS (rgn) + b]);
deaths_in_region[rgn] = count_or_remove_death_notes (blocks, 1);
}
I'm fairly certain that this _shouldn't_ happen, since I don't think
that live_at_start should change at region heads. Not sure what the
- best way to test for this kind of thing... */
+ best way to test for this kind of thing... */
allocate_reg_life_data ();
compute_bb_for_insn (max_uid);
/* In the single block case, the count of registers that died should
not have changed during the schedule. */
if (count_or_remove_death_notes (blocks, 0) != deaths_in_region[rgn])
- abort ();
+ abort ();
#endif
}
if (any_large_regions)
{
update_life_info (large_region_blocks, UPDATE_LIFE_GLOBAL,
- PROP_DEATH_NOTES | PROP_REG_INFO);
+ PROP_DEATH_NOTES | PROP_REG_INFO);
}
/* Reposition the prologue and epilogue notes in case we moved the
{
if (reload_completed == 0 && flag_schedule_interblock)
{
- fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n",
+ fprintf (dump,
+ "\n;; Procedure interblock/speculative motions == %d/%d \n",
nr_inter, nr_spec);
}
else
projects / platform / upstream / gcc.git / commitdiff