[Hexagon] Fix fshl/fshr -> combine() bug identified in D75114
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 6 Mar 2020 17:22:55 +0000 (17:22 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 6 Mar 2020 17:23:10 +0000 (17:23 +0000)
llvm/lib/Target/Hexagon/HexagonPatterns.td
llvm/test/CodeGen/Hexagon/funnel-shift.ll

index 2bfd8d7..cc10627 100644 (file)
@@ -1095,7 +1095,7 @@ def Divu64_8: SDNodeXForm<imm, [{
 // Special cases:
 let AddedComplexity = 100 in {
   def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)),
-           (A2_combine_hl I32:$Rs, I32:$Rt)>;
+           (A2_combine_lh I32:$Rs, I32:$Rt)>;
   def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S),
            (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>;
 }
@@ -1129,7 +1129,7 @@ def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
 // Special cases:
 let AddedComplexity = 100 in {
   def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)),
-           (A2_combine_hl I32:$Rs, I32:$Rt)>;
+           (A2_combine_lh I32:$Rs, I32:$Rt)>;
   def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S),
            (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>;
 }
index 4790681..b4b8f47 100644 (file)
@@ -257,7 +257,7 @@ b0:
 }
 
 ; CHECK-LABEL: f30:
-; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
+; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
 define i32 @f30(i32 %a0, i32 %a1) #1 {
 b0:
   %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 16)
@@ -265,7 +265,7 @@ b0:
 }
 
 ; CHECK-LABEL: f31:
-; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
+; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
 define i32 @f31(i32 %a0, i32 %a1) #1 {
 b0:
   %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 16)