Enable L2 cache for MPC8568MDS board
authorHaiying Wang <Haiying.Wang@freescale.com>
Thu, 23 Aug 2007 19:20:54 +0000 (15:20 -0400)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Wed, 29 Aug 2007 05:11:44 +0000 (00:11 -0500)
The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
cpu/mpc85xx/cpu_init.c
include/configs/MPC8568MDS.h

index 7b99610..79ad20c 100644 (file)
@@ -247,7 +247,7 @@ int cpu_init_r(void)
        switch (cache_ctl & 0x30000000) {
        case 0x20000000:
                if (ver == SVR_8548 || ver == SVR_8548_E ||
-                   ver == SVR_8544) {
+                   ver == SVR_8544 || ver == SVR_8568_E) {
                        printf ("L2 cache 512KB:");
                        /* set L2E=1, L2I=1, & L2SRAM=0 */
                        cache_ctl = 0xc0000000;
index d5a14fc..ba744e9 100644 (file)
@@ -63,9 +63,9 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-/*#define CONFIG_L2_CACHE*/                        /* toggle L2 cache  */
-#define CONFIG_BTB                                             /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING              /* toggle addr streaming   */
+#define CONFIG_L2_CACHE                                /* toggle L2 cache      */
+#define CONFIG_BTB                             /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING                  /* toggle addr streaming   */
 
 /*
  * Only possible on E500 Version 2 or newer cores.