[AArch64][GlobalISel] Fix i1 arguments not being zero-extended as required by ABI.

Fixes PR41001.

llvm-svn: 355745

diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
index 7f8cb7f..8a00a3f 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -363,6 +363,9 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                       [&](unsigned Reg, uint64_t Offset) {
                         MIRBuilder.buildExtract(Reg, OrigArg.Reg, Offset);
                       });
+    // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
+    if (OrigArg.Ty->isIntegerTy(1))
+      SplitArgs.back().Flags.setZExt();
   }
 
   // Find out which ABI gets to decide where things go.

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 81505b8..57575ed 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -2350,3 +2350,12 @@ define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) {
 }
 
 declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32*) #3
+
+define void @test_i1_arg_zext(void (i1)* %f) {
+; CHECK-LABEL: name: test_i1_arg_zext
+; CHECK: [[I1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[I1]](s1)
+; CHECK: $w0 = COPY [[ZEXT]](s32)
+  call void %f(i1 true)
+  ret void
+}