tu: fix rast state allocation size on a6xx gen4

A few regs were added without changing the size of draw state.

Fixes: 4e05338d99abbf2858a0d8444ffc53028fe23051 ("turnip: Rast updates for a6xx gen4")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13644>

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 0072562..dc8d663 100644 (file)
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2779,7 +2779,9 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
    }
 
    struct tu_cs cs;
-   uint32_t cs_size = 9 + (builder->emit_msaa_state ? 11 : 0);
+   uint32_t cs_size = 9 +
+      (builder->device->physical_device->info->a6xx.has_shading_rate ? 8 : 0) +
+      (builder->emit_msaa_state ? 11 : 0);
    pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, cs_size);
 
    tu_cs_emit_regs(&cs,