bool RegBankSelected = false;
bool Selected = false;
// Register information
- bool IsSSA = false;
bool TracksRegLiveness = false;
bool TracksSubRegLiveness = false;
std::vector<VirtualRegisterDefinition> VirtualRegisters;
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);
- YamlIO.mapOptional("isSSA", MF.IsSSA);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
YamlIO.mapOptional("registers", MF.VirtualRegisters);
return false;
}
+static bool isSSA(const MachineFunction &MF) {
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
+ if (!MRI.hasOneDef(Reg) && !MRI.def_empty(Reg))
+ return false;
+ }
+ return true;
+}
+
void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
+ MachineFunctionProperties &Properties = MF.getProperties();
if (!hasPHI(MF))
- MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+ Properties.set(MachineFunctionProperties::Property::NoPHIs);
+
+ if (isSSA(MF))
+ Properties.set(MachineFunctionProperties::Property::IsSSA);
+ else
+ Properties.clear(MachineFunctionProperties::Property::IsSSA);
}
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- assert(RegInfo.isSSA());
- if (!YamlMF.IsSSA)
- RegInfo.leaveSSA();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
RegInfo.invalidateLiveness();
void MIRPrinter::convert(yaml::MachineFunction &MF,
const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI) {
- MF.IsSSA = RegInfo.isSSA();
MF.TracksRegLiveness = RegInfo.tracksLiveness();
MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
FirstTerminator = nullptr;
- if (MRI->isSSA()) {
+ if (!MF->getProperties().hasProperty(
+ MachineFunctionProperties::Property::NoPHIs)) {
// If this block has allocatable physical registers live-in, check that
// it is an entry block or landing pad.
for (const auto &LI : MBB->liveins()) {
# Also check that we constrain the register class of the COPY to GPR32.
# CHECK-LABEL: name: add_s32_gpr
name: add_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for 64-bit operations.
# CHECK-LABEL: name: add_s64_gpr
name: add_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_SUB operations.
# CHECK-LABEL: name: sub_s32_gpr
name: sub_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_SUB operations.
# CHECK-LABEL: name: sub_s64_gpr
name: sub_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_OR operations.
# CHECK-LABEL: name: or_s32_gpr
name: or_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_OR operations.
# CHECK-LABEL: name: or_s64_gpr
name: or_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_XOR operations.
# CHECK-LABEL: name: xor_s32_gpr
name: xor_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_XOR operations.
# CHECK-LABEL: name: xor_s64_gpr
name: xor_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_AND operations.
# CHECK-LABEL: name: and_s32_gpr
name: and_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_AND operations.
# CHECK-LABEL: name: and_s64_gpr
name: and_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_SHL operations.
# CHECK-LABEL: name: shl_s32_gpr
name: shl_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_SHL operations.
# CHECK-LABEL: name: shl_s64_gpr
name: shl_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_LSHR operations.
# CHECK-LABEL: name: lshr_s32_gpr
name: lshr_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_LSHR operations.
# CHECK-LABEL: name: lshr_s64_gpr
name: lshr_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_ASHR operations.
# CHECK-LABEL: name: ashr_s32_gpr
name: ashr_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_ASHR operations.
# CHECK-LABEL: name: ashr_s64_gpr
name: ashr_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# there is only MADDWrrr, and we have to use the WZR physreg.
# CHECK-LABEL: name: mul_s32_gpr
name: mul_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as mul_s32_gpr for the s64 type.
# CHECK-LABEL: name: mul_s64_gpr
name: mul_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_SDIV operations.
# CHECK-LABEL: name: sdiv_s32_gpr
name: sdiv_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_SDIV operations.
# CHECK-LABEL: name: sdiv_s64_gpr
name: sdiv_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s32_gpr, for G_UDIV operations.
# CHECK-LABEL: name: udiv_s32_gpr
name: udiv_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Same as add_s64_gpr, for G_UDIV operations.
# CHECK-LABEL: name: udiv_s64_gpr
name: udiv_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
# Check that we select a s32 FPR G_FADD into FADDSrr.
# CHECK-LABEL: name: fadd_s32_gpr
name: fadd_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fadd_s64_gpr
name: fadd_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fsub_s32_gpr
name: fsub_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fsub_s64_gpr
name: fsub_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fmul_s32_gpr
name: fmul_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fmul_s64_gpr
name: fmul_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fdiv_s32_gpr
name: fdiv_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: fdiv_s64_gpr
name: fdiv_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: unconditional_br
name: unconditional_br
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: load_s64_gpr
name: load_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: load_s32_gpr
name: load_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: store_s64_gpr
name: store_s64_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: store_s32_gpr
name: store_s32_gpr
-isSSA: true
legalized: true
regBankSelected: true
---
# CHECK-LABEL: name: frame_index
name: frame_index
-isSSA: true
legalized: true
regBankSelected: true
# CHECK: legalized: true
# CHECK-NEXT: regBankSelected: true
# CHECK-NEXT: selected: true
-# CHECK-NEXT: isSSA: true
name: selected_property
-isSSA: true
legalized: true
regBankSelected: true
selected: false
# Check that we assign a relevant register bank for %0.
# Based on the type i32, this should be gpr.
name: defaultMapping
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# Based on the type <2 x i32>, this should be fpr.
# FPR is used for both floating point and vector registers.
name: defaultMappingVector
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# Indeed based on the source of the copy it should live
# in FPR, but at the use, it should be GPR.
name: defaultMapping1Repair
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# Check that we repair the assignment for %0 differently for both uses.
name: defaultMapping2Repairs
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# requires that it lives in GPR. Make sure regbankselect
# fixes that.
name: defaultMappingDefRepair
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
---
# Check that we are able to propagate register banks from phis.
name: phiPropagation
-isSSA: true
legalized: true
tracksRegLiveness: true
# CHECK: registers:
---
# Make sure we can repair physical register uses as well.
name: defaultMappingUseRepairPhysReg
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
---
# Make sure we can repair physical register defs.
name: defaultMappingDefRepairPhysReg
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# Check that the greedy mode is able to switch the
# G_OR instruction from fpr to gpr.
name: greedyMappingOr
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# G_OR instruction from fpr to gpr, while still honoring
# %2 constraint.
name: greedyMappingOrWithConstraints
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
---
# CHECK-LABEL: name: ignoreTargetSpecificInst
name: ignoreTargetSpecificInst
-isSSA: true
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-LABEL: name: regBankSelected_property
# CHECK: legalized: true
# CHECK: regBankSelected: true
-# CHECK: isSSA: true
name: regBankSelected_property
-isSSA: true
legalized: true
regBankSelected: false
body: |
---
name: test_scalar_add_big
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_scalar_add_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_vector_add
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_scalar_and_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_icmp
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_constant
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_fconstant
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_copy
-isSSA: true
registers:
- { id: 0, class: _ }
body: |
---
name: test_targetspecific
-isSSA: true
body: |
bb.0:
; CHECK-LABEL: name: test_targetspecific
---
name: test_load
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_store
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_scalar_mul_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_scalar_or_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# Check that we set the "legalized" property.
# CHECK-LABEL: name: legalized_property
# CHECK: legalized: true
-# CHECK: isSSA: true
name: legalized_property
-isSSA: true
legalized: false
body: |
bb.0:
---
name: test_simple
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_scalar_sub_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
---
name: test_scalar_xor_small
-isSSA: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: instruction: %vreg0<def>(64) = COPY
# CHECK: operand 0: %vreg0<def>
name: test
-isSSA: true
regBankSelected: true
registers:
- { id: 0, class: _ }
---
name: test
-isSSA: true
regBankSelected: true
selected: true
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
liveins:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
liveins:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
frameInfo:
# CHECK: S_NOP 0, implicit %4.sub1
# CHECK: S_NOP 0, implicit undef %5.sub0
name: test0
-isSSA: true
registers:
- { id: 0, class: sreg_32 }
- { id: 1, class: sreg_32 }
# CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
# CHECK: S_NOP 0, implicit undef %10
name: test1
-isSSA: true
registers:
- { id: 0, class: sreg_128 }
- { id: 1, class: sreg_128 }
# CHECK: S_NOP 0, implicit %16.sub1
name: test2
-isSSA: true
registers:
- { id: 0, class: sreg_32 }
- { id: 1, class: sreg_32 }
# CHECK: %1 = COPY %vcc
# CHECK: S_NOP 0, implicit %1
name: test3
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_64 }
# CHECK: %1 = IMPLICIT_DEF
# CHECK: S_NOP 0, implicit undef %1
name: test4
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_64 }
# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
# CHECK: S_NOP 0, implicit %1.sub1
name: test5
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
# CHECK: S_NOP 0, implicit %4.sub0
# CHECK: S_NOP 0, implicit undef %4.sub3
name: loop0
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
# CHECK: bb.2:
# CHECK: S_NOP 0, implicit %6.sub3
name: loop1
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
# CHECK: S_NOP 0, implicit %2.sub2
# CHECK: S_NOP 0, implicit %2.sub3
name: loop2
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_32 }
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
---
name: baz
-isSSA: true
registers:
- { id: 0, class: _ }
body: |
---
name: bar
-isSSA: true
registers:
- { id: 0, class: gpr }
body: |
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: false
tracksSubRegLiveness: false
liveins:
# CHECK: LDRWui %x0, 1
# CHECK: STRWui %w1, %x0, 2
name: load_imp-def
-isSSA: true
body: |
bb.0.entry:
liveins: %w1, %x0
...
---
name: stack_local
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64common }
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
...
---
name: test
-isSSA: true
tracksRegLiveness: true
# CHECK: frameInfo:
...
---
name: test2
-isSSA: true
tracksRegLiveness: true
# CHECK: test2
...
---
# CHECK: name: foo
-# CHECK: isSSA: false
-# CHECK-NEXT: tracksRegLiveness: false
+# CHECK: tracksRegLiveness: false
# CHECK-NEXT: tracksSubRegLiveness: false
# CHECK: ...
name: foo
...
---
# CHECK: name: bar
-# CHECK: isSSA: false
-# CHECK-NEXT: tracksRegLiveness: true
+# CHECK: tracksRegLiveness: true
# CHECK-NEXT: tracksSubRegLiveness: true
# CHECK: ...
name: bar
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: true
body: |
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
...
---
name: main
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
---
name: test_vregs
-isSSA: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _ }
# CHECK-NEXT: - { id: 1, class: _ }
---
name: test_unsized
-isSSA: true
body: |
bb.0:
successors: %bb.0
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test_typed_immediates
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: foo
-isSSA: true
tracksRegLiveness: true
frameInfo:
maxAlignment: 16
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: foo
-isSSA: true
tracksRegLiveness: true
frameInfo:
maxAlignment: 16
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
# CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
# CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
# CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200'
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
---
name: test_size_physreg
-isSSA: true
registers:
body: |
bb.0.entry:
---
name: test_size_regclass
-isSSA: true
registers:
- { id: 0, class: gr32 }
body: |
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: t
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: test
-isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: bar
-isSSA: true
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
...
---
name: foo
-isSSA: true
tracksRegLiveness: true
# CHECK: name: foo
# CHECK: registers:
exposesReturnsTwice: false
hasInlineAsm: true
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
frameInfo:
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
---
name: foo
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movb_killed
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movb_impuse
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movb_impdef_gr64
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movb_impdef_gr32
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movb_impdef_gr16
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movw_impdef_gr32
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
---
name: test_movw_impdef_gr64
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
name: imp_null_check_with_bitwise_op_1
alignment: 4
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: true
-isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: false
liveins:
projects / platform / upstream / llvm.git / commitdiff