ARM: dts: at91: sama7g5: Add QSPI0 and OSPI1 nodes

sama7g5 embedds an OSPI and a QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
   and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index b951aff..4a3c675 100644 (file)
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -91,6 +91,32 @@
                                #clock-cells = <1>;
                        };
 
+                       qspi0: spi@e080c000 {
+                               compatible = "microchip,sama7g5-ospi";
+                               reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
+                               reg-names = "qspi_base", "qspi_mmap";
+                               clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
+                               clock-names = "pclk", "gclk";
+                               assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
+                               assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       qspi1: spi@e0810000 {
+                               compatible = "microchip,sama7g5-qspi";
+                               reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
+                               reg-names = "qspi_base", "qspi_mmap";
+                               clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
+                               clock-names = "pclk", "gclk";
+                               assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
+                               assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        sdmmc0: sdio-host@e1204000 {
                                compatible = "microchip,sama7g5-sdhci";
                                reg = <0xe1204000 0x300>;