clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
authorTuomas Tynkkynen <ttynkkynen@nvidia.com>
Wed, 13 May 2015 14:58:43 +0000 (17:58 +0300)
committerThierry Reding <treding@nvidia.com>
Thu, 16 Jul 2015 08:40:20 +0000 (10:40 +0200)
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra-super-gen4.c

index feb3201..f1f4410 100644 (file)
@@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
 
 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
                                        "pll_p", "pll_p_out4", "unused",
-                                       "unused", "pll_x" };
+                                       "unused", "pll_x", "unused", "unused",
+                                       "unused", "unused", "unused", "unused",
+                                       "dfllCPU_out" };
 
 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
                                         "pll_p", "pll_p_out4", "unused",