drm/i915/tgl: Wa_1607138336
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Tue, 15 Oct 2019 15:44:47 +0000 (18:44 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 15 Oct 2019 17:25:14 +0000 (18:25 +0100)
Avoid possible deadlock on context switch.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-9-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/i915_reg.h

index 4f9be2e..4837251 100644 (file)
@@ -1281,6 +1281,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_masked_en(wal,
                             GEN9_CS_DEBUG_MODE1,
                             FF_DOP_CLOCK_GATE_DISABLE);
+
+               /* Wa_1607138336:tgl */
+               wa_write_or(wal,
+                           GEN9_CTX_PREEMPT_REG,
+                           GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
        }
 
        if (IS_GEN(i915, 11)) {
index 449648a..baf5939 100644 (file)
@@ -7678,6 +7678,8 @@ enum {
 #define GEN9_CS_DEBUG_MODE1            _MMIO(0x20ec)
 #define   FF_DOP_CLOCK_GATE_DISABLE    REG_BIT(1)
 #define GEN9_CTX_PREEMPT_REG           _MMIO(0x2248)
+#define   GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
+
 #define GEN8_CS_CHICKEN1               _MMIO(0x2580)
 #define GEN9_PREEMPT_3D_OBJECT_LEVEL           (1 << 0)
 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)       (((hi) << 2) | ((lo) << 1))