else
ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
U_BOOT_ITS := u-boot.its
-ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
-U_BOOT_ITS_DEPS += u-boot-nodtb.bin
-endif
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
U_BOOT_ITS_DEPS += u-boot
endif
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
- imx6ul-pico-pi.dtb
+ imx6ul-pico-pi.dtb \
+ imx6ul-kontron-n631x-s.dtb \
+ imx6ull-kontron-n641x-s.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
+ imx8mm-kontron-n801x-s.dtb \
+ imx8mm-kontron-n801x-s-lvds.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
+
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
targets += $(dtb-y)
soc {
u-boot,dm-pre-reloc;
- aips@50000000 {
+ bus@50000000 {
u-boot,dm-pre-reloc;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
+ broken-cd;
status = "okay";
};
clock-names = "core_clk", "mem_iface_clk";
};
- aips@50000000 { /* AIPS1 */
+ bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips@60000000 { /* AIPS2 */
+ bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2020 Foundries.IO
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&wdog1 {
+ status = "okay";
+ u-boot,dm-spl;
+};
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
soc {
u-boot,dm-pre-reloc;
- aips-bus@2100000 {
+ bus@2100000 {
u-boot,dm-pre-reloc;
};
};
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator@3 {
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ reg_usb_h1_vbus: regulator-usbh1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&gpmi {
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
- status = "okay"; };
+ status = "okay";
+};
&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
&usbh1 {
vbus-supply = <®_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
+ gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
&usbh1 {
vbus-supply = <®_usb_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
>;
};
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ >;
+ };
+
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
u-boot,dm-spl;
u-boot,dm-pre-reloc;
- aips-bus@2000000 {
+ bus@2000000 {
u-boot,dm-spl;
spba-bus@2000000 {
u-boot,dm-spl;
};
};
- aips-bus@2100000 {
+ bus@2100000 {
u-boot,dm-spl;
};
};
status = "disabled";
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips-bus@2100000 { /* AIPS2 */
+ bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2100000 {
+ bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
- aips1: aips-bus@02000000 {
+ aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@02100000 {
+ aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
arm,data-latency = <4 2 3>;
};
- aips1: aips-bus@02000000 {
+ aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@02100000 {
+ aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-kontron-n631x-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N631X S";
+ compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som",
+ "fsl,imx6ul";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N631X SOM";
+ compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "SPL";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x11000>;
+ filename = "u-boot.img";
+ };
+ };
+};
+
+#endif /* CONFIG_FIT */
+
+/*
+ * To make the PHYs work, we need to set the reset pin once. Afterwards
+ * in Linux we can't assign the shared reset GPIO to the PHYs, as this
+ * would cause Linux to reset both PHYs every time one of them gets
+ * reinitialized.
+ *
+ * Also we disable the second ethernet as it currently doesn't work with
+ * the devicetree setup in U-Boot.
+ */
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ status = "disabled";
+ /delete-property/ phy-handle;
+ /delete-node/ mdio;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6ul-kontron-n6x1x-som.dtsi"
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ device_type = "memory";
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_out>;
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
+ >;
+ };
+
+ pinctrl_enet1_mdio: enet1mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_reset_out: rstoutgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+};
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-n641x-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N641X S";
+ compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som",
+ "fsl,imx6ull";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N641X SOM";
+ compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull";
+};
/ {
soc {
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
<0x31006000 0x2000>;
};
- aips1: aips-bus@30000000 {
+ aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips2: aips-bus@30400000 {
+ aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips3: aips-bus@30800000 {
+ aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl2.bin";
+ };
+ };
+
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf", "fip";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mm-cl-iot-gate.dts"
};
};
- fip {
- description = "Trusted Firmware FIP";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x40310000>;
-
- fip_blob: blob-ext{
- filename = "fip.bin";
- };
- };
-
fdt {
description = "NAME";
type = "flat_dt";
conf {
description = "NAME";
firmware = "uboot";
- loadables = "atf", "fip";
+ loadables = "atf";
fdt = "fdt";
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-n801x-s.dts"
+
+/ {
+ model = "Kontron i.MX8MM N801X S LVDS";
+ compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
+ power-supply = <®_vdd_24v>;
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <100>;
+ status = "okay";
+ };
+
+ reg_panel_pwr: regpanel-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_pwr";
+ regulator-always-on;
+ gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_rst: regpanel-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_rst";
+ regulator-always-on;
+ gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_stby: regpanel-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_stby";
+ regulator-always-on;
+ gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_hinv: regpanel-hinv {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_hinv";
+ regulator-always-on;
+ gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel_vinv: regpanel-vinv {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_panel_vinv";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vdd_24v: regulator-24v {
+ compatible = "regulator-fixed";
+ regulator-name = "reg-vdd-24v";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "okay";
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ gt911@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <22 8>;
+ reset-gpios = <&gpio3 23 0>;
+ irq-gpios = <&gpio3 22 0>;
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_panel: panelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
+ MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&fec1 {
+ phy-mode = "rgmii-rxid";
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c2 {
+ status = "okay";
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ecspi1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ /* Disable Pullup for SD_VSEL */
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
+ >;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pca9450 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&ecspi1 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x57c00>;
+ filename = "u-boot.itb";
+ };
+ };
+
+ u-boot-update {
+ filename = "firmware-update.itb";
+
+ fit {
+ description = "Configuration for firmware update file";
+
+ images {
+ flash-bin {
+ description = "U-Boot flash image";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compress = "none";
+ load = <0>; /* unused */
+
+ blob {
+ filename = "flash.bin";
+ };
+
+ };
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mm-kontron-n801x-som.dtsi"
+#include <dt-bindings/net/mscc-phy-vsc8531.h>
+
+/ {
+ model = "Kontron i.MX8MM N801X S";
+ compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+
+ aliases {
+ ethernet1 = &usbnet;
+ };
+
+ /* fixed crystal dedicated to mcp2515 */
+ osc_can: clock-osc-can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "osc-can";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ label = "led3";
+ gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led4 {
+ label = "led4";
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ label = "led5";
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ label = "led6";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm2 0 5000 0>;
+ };
+
+ reg_rst_eth2: regulator-rst-eth2 {
+ compatible = "regulator-fixed";
+ regulator-name = "rst-usb-eth2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_eth2>;
+ gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_vdd_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&osc_can>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <®_vdd_3v3>;
+ xceiver-supply = <®_vdd_5v>;
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-connection-type = "rgmii-rxid";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.0570";
+ reg = <0>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <100>;
+ reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-0-combine-disable;
+ };
+ };
+};
+
+&gpio4 {
+ dsi_mux_sel: dsi_mux_sel {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "dsi-mux-sel";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_sel>;
+ };
+
+ dsi_mux_oe {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "dsi-mux-oe";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_oe>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ over-current-active-low;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbnet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_nvcc_sd>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio>;
+
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
+ >;
+ };
+
+ pinctrl_dsi_sel: dsiselgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
+ >;
+ };
+
+ pinctrl_dsi_oe: dsioegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usb_eth2: usbeth2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N801X SoM";
+ compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ /*
+ * There are multiple SoM flavors with different DDR sizes.
+ * The smallest is 1GB. For larger sizes the bootloader will
+ * update the reg property.
+ */
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ reg = <0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <850000>;
+ nxp,dvs-standby-voltage = <800000>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_vdd_dram: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_1v8: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_dram: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_snvs: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_snvs: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdda: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_phy: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_sd: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
* Copyright 2021 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <1>;
};
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
u-boot,dm-spl;
};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
reg = <0x69>;
regulators {
+ /* vdd_0p95: DRAM/GPU/VPU */
buck1 {
- regulator-name = "vdd_0p95";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-max-microamp = <2500000>;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_soc */
buck2 {
- regulator-name = "vdd_soc";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck2";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
- regulator-max-microamp = <1000000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_arm */
buck3_reg: buck3 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <805000>;
+ regulator-name = "buck3";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-max-microamp = <2200000>;
- regulator-boot-on;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
+ regulator-always-on;
};
+ /* vdd_1p8 */
buck4 {
- regulator-name = "vdd_1p8";
+ regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-max-microamp = <500000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* nvcc_snvs_1p8 */
ldo1 {
- regulator-name = "nvcc_snvs_1p8";
+ regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-max-microamp = <300000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_snvs_0p8 */
ldo2 {
- regulator-name = "vdd_snvs_0p8";
+ regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_0p9 */
ldo3 {
- regulator-name = "vdd_0p95";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
regulator-boot-on;
+ regulator-always-on;
};
+ /* vdd_1p8 */
ldo4 {
- regulator-name = "vdd_1p8";
+ regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
+ regulator-always-on;
};
};
};
* Copyright 2020 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <1>;
};
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
>;
};
};
-
-&cpu_alert0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
-};
-
-&cpu_crit0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "critical";
-};
* Copyright 2021 Gateworks Corporation
*/
-#include "imx8mm-u-boot.dtsi"
-
-&gpio1 {
- u-boot,dm-spl;
-};
-
-&gpio2 {
- u-boot,dm-spl;
-};
-
-&gpio3 {
- u-boot,dm-spl;
-};
-
-&gpio4 {
- u-boot,dm-spl;
-};
-
-&gpio5 {
- u-boot,dm-spl;
-};
-
-&uart2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-spl;
-};
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
-
-&i2c1 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c1 {
- u-boot,dm-spl;
-};
-
-&i2c2 {
- u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
- u-boot,dm-spl;
-};
+#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
>;
};
};
-
-&cpu_alert0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
-};
-
-&cpu_crit0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "critical";
-};
&fec1 {
fsl,magic-packet;
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_ethphy>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
};
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot.itb";
+ offset = <0x58000>;
+ };
+ };
};
compatible = "simple-bus";
ranges;
- aips0: aips-bus@40000000 {
+ aips0: bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- aips1: aips-bus@40080000 {
+ aips1: bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_IMX8M
-#define PAD_CTL_DSE0 (0x0 << 0)
-#define PAD_CTL_DSE1 (0x1 << 0)
-#define PAD_CTL_DSE2 (0x2 << 0)
-#define PAD_CTL_DSE3 (0x3 << 0)
-#define PAD_CTL_DSE4 (0x4 << 0)
-#define PAD_CTL_DSE5 (0x5 << 0)
-#define PAD_CTL_DSE6 (0x6 << 0)
-#define PAD_CTL_DSE7 (0x7 << 0)
-
#define PAD_CTL_FSEL0 (0x0 << 3)
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
#define PAD_CTL_PUE (0x1 << 6)
#define PAD_CTL_HYS (0x1 << 7)
#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+#define PAD_CTL_DSE1 (0x0 << 1)
+#define PAD_CTL_DSE2 (0x2 << 1)
+#define PAD_CTL_DSE4 (0x1 << 1)
+#define PAD_CTL_DSE6 (0x3 << 1)
#define PAD_CTL_PE (0x1 << 8)
#else
+#define PAD_CTL_DSE0 (0x0 << 0)
+#define PAD_CTL_DSE1 (0x1 << 0)
+#define PAD_CTL_DSE2 (0x2 << 0)
+#define PAD_CTL_DSE3 (0x3 << 0)
+#define PAD_CTL_DSE4 (0x4 << 0)
+#define PAD_CTL_DSE5 (0x5 << 0)
+#define PAD_CTL_DSE6 (0x6 << 0)
+#define PAD_CTL_DSE7 (0x7 << 0)
#define PAD_CTL_LVTTL (0x1 << 8)
#endif
config IMX_HAB
bool "Support i.MX HAB features"
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP
select FSL_CAAM if HAS_CAAM
imply CMD_DEKBLOB if HAS_CAAM
help
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
-IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
-DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
+DEPFILE_EXISTS := 0
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
ifdef CONFIG_ARM64
ifeq ($(CONFIG_ARCH_IMX8M), y)
-SPL:
+
+SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
flash.bin: MKIMAGEOUTPUT = flash.log
+spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+
spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
-ifeq ($(DEPFILE_EXISTS),0)
- $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
-endif
flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
$(call if_changed,mkimage)
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_KONTRON_MX8MM
+ bool "Kontron Electronics N80xx"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+
+config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
+ bool "CompuLab iot-gate-imx8 with optee support"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
source "board/beacon/imx8mm/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
+source "board/kontron/sl-mx8mm/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
ulong board_get_usable_ram_top(ulong total_size)
{
+ ulong top_addr = PHYS_SDRAM + gd->ram_size;
+
/*
* Some IPs have their accessible address space restricted by
* the interconnect. Let's make sure U-Boot only ever uses the
* space below the 4G address boundary (which is 3GiB big),
* even when the effective available memory is bigger.
*/
- if (PHYS_SDRAM + gd->ram_size > 0x80000000)
- return 0x80000000;
+ if (top_addr > 0x80000000)
+ top_addr = 0x80000000;
+
+ /*
+ * rom_pointer[0] stores the TEE memory start address.
+ * rom_pointer[1] stores the size TEE uses.
+ * We need to reserve the memory region for TEE.
+ */
+ if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
+ top_addr = rom_pointer[0];
- return PHYS_SDRAM + gd->ram_size;
+ return top_addr;
}
static u32 get_cpu_variant_type(u32 type)
+++ /dev/null
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for i.MX8MQ boards with
-# ARM Trusted Firmware and multiple device trees (given on the command line)
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$BL31" ] && BL31="bl31.bin"
-[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
-[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
-[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
-
-if [ ! -f $BL31 ]; then
- echo "ERROR: BL31 file $BL31 NOT found" >&2
- exit 0
-else
- echo "$BL31 size: " >&2
- stat -c %s $BL31 >&2
-fi
-
-BL32="tee.bin"
-
-if [ ! -f $BL32 ]; then
- BL32=/dev/null
-else
- echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
- echo "$BL32 size: " >&2
- stat -c %s $BL32 >&2
-fi
-
-BL33="u-boot-nodtb.bin"
-
-if [ ! -f $BL33 ]; then
- echo "ERROR: $BL33 file NOT found" >&2
- exit 0
-else
- echo "u-boot-nodtb.bin size: " >&2
- stat -c %s u-boot-nodtb.bin >&2
-fi
-
-for dtname in $*
-do
- echo "$dtname size: " >&2
- stat -c %s $dtname >&2
-done
-
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
- description = "Configuration to load ATF before U-Boot";
-
- images {
- uboot@1 {
- description = "U-Boot (64-bit)";
- os = "u-boot";
- data = /incbin/("$BL33");
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <$BL33_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt@$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
-cat << __HEADER_EOF
- atf@1 {
- description = "ARM Trusted Firmware";
- os = "arm-trusted-firmware";
- data = /incbin/("$BL31");
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <$ATF_LOAD_ADDR>;
- entry = <$ATF_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-if [ -f $BL32 ]; then
-cat << __HEADER_EOF
- tee@1 {
- description = "TEE firmware";
- data = /incbin/("$BL32");
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <$TEE_LOAD_ADDR>;
- entry = <$TEE_LOAD_ADDR>;
- };
-__HEADER_EOF
-fi
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config@1";
-
-__CONF_HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-if [ -f $BL32 ]; then
-cat << __CONF_SECTION_EOF
- config@$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1", "tee@1";
- fdt = "fdt@$cnt";
- };
-__CONF_SECTION_EOF
-else
-cat << __CONF_SECTION1_EOF
- config@$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot@1";
- loadables = "atf@1";
- fdt = "fdt@$cnt";
- };
-__CONF_SECTION1_EOF
-fi
-cnt=$((cnt+1))
-done
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
imply CMD_SATA
imply CMD_SPL
+config TARGET_KONTRON_MX6UL
+ bool "Kontron Electronics SL/BL i.MX6UL/ULL (N63xx/N64xx)"
+ depends on MX6UL
+ select BINMAN
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
+source "board/kontron/sl-mx6ul/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/softing/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
static void disable_wdog(u32 wdog_base)
{
- writel(UNLOCK_WORD0, (wdog_base + 0x04));
- writel(UNLOCK_WORD1, (wdog_base + 0x04));
- writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
- writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
- writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
-
- writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
- writel(REFRESH_WORD1, (wdog_base + 0x04));
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ dmb();
+ __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+ __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ if (!(val_cs & 800)) {
+ dmb();
+ __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
+ __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x800));
+ }
+ dmb();
+ __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */
+ __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */
+ __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x400));
}
void init_wdog(void)
}
#endif
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ int align_len = ARCH_DMA_MINALIGN - 1;
+
+ /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address
+ * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust
+ * the bl_len to align with SD/MMC.
+ */
+ if (bl_len < 512)
+ bl_len = 512;
+
+ return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len -
+ align_len) & ~align_len);
+}
#endif
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
return 0;
}
#endif
+
+/*
+ * read the address where the IVT header must sit
+ * from IVT image header, loaded from SPL into
+ * an malloced buffer and copy the IVT header
+ * to this address
+ */
+void *spl_load_simple_fit_fix_load(const void *fit)
+{
+ struct ivt *ivt;
+ unsigned long new;
+ unsigned long offset;
+ unsigned long size;
+ u8 *tmp = (u8 *)fit;
+
+ offset = ALIGN(fdt_totalsize(fit), 0x1000);
+ size = ALIGN(fdt_totalsize(fit), 4);
+ size = board_spl_fit_size_align(size);
+ tmp += offset;
+ ivt = (struct ivt *)tmp;
+ if (ivt->hdr.magic != IVT_HEADER_MAGIC) {
+ debug("no IVT header found\n");
+ return (void *)fit;
+ }
+ debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size);
+ debug("%s: ivt self: %x\n", __func__, ivt->self);
+ new = ivt->self;
+ new -= offset;
+ debug("%s: new %lx\n", __func__, new);
+ memcpy((void *)new, fit, size);
+
+ return (void *)new;
+}
-if TARGET_IMX8MM_CL_IOT_GATE
+if TARGET_IMX8MM_CL_IOT_GATE || TARGET_IMX8MM_CL_IOT_GATE_OPTEE
config SYS_BOARD
default "imx8mm-cl-iot-gate"
F: board/compulab/imx8mm-cl-iot-gate/
F: include/configs/imx8mm-cl-iot-gate.h
F: configs/imx8mm-cl-iot-gate_defconfig
+F: configs/imx8mm-cl-iot-gate-optee_defconfig
#include <common.h>
#include <env.h>
+#include <hang.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include "ddr/ddr.h"
+
DECLARE_GLOBAL_DATA_PTR;
+int board_phys_sdram_size(phys_size_t *size)
+{
+ struct lpddr4_tcm_desc *lpddr4_tcm_desc =
+ (struct lpddr4_tcm_desc *)TCM_DATA_CFG;
+
+ switch (lpddr4_tcm_desc->size) {
+ case 4096:
+ case 2048:
+ case 1024:
+ *size = (1L << 20) * lpddr4_tcm_desc->size;
+ break;
+ default:
+ printf("%s: DRAM size %uM is not supported\n",
+ __func__,
+ lpddr4_tcm_desc->size);
+ hang();
+ break;
+ };
+
+ return 0;
+}
+
static int setup_fec(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x920000
+LOADER u-boot-spl-ddr.bin 0x920000
struct ventana_board_info ventana_info;
static int board_type;
-#ifdef CONFIG_USB_EHCI_MX6
-/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
-int board_ehci_hcd_init(int port)
-{
- int gpio;
-
- /* USB HUB is always on P1 */
- if (port == 0)
- return 0;
-
- /* Reset USB HUB */
- switch (board_type) {
- case GW53xx:
- case GW552x:
- case GW5906:
- gpio = (IMX_GPIO_NR(1, 9));
- break;
- case GW54proto:
- case GW54xx:
- gpio = (IMX_GPIO_NR(1, 16));
- break;
- default:
- return 0;
- }
-
- /* request and toggle hub rst */
- gpio_request(gpio, "usb_hub_rst#");
- gpio_direction_output(gpio, 0);
- mdelay(2);
- gpio_set_value(gpio, 1);
-
- return 0;
-}
-#endif /* CONFIG_USB_EHCI_MX6 */
-
/* configure eth0 PHY board-specific LED behavior */
int board_phy_config(struct phy_device *phydev)
{
imx_enable_hdmi_phy();
}
-static int detect_i2c(struct display_info_t const *dev)
+static int detect_lvds(struct display_info_t const *dev)
{
+ /* only the following boards support LVDS connectors */
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ case GW560x:
+ case GW5905:
+ case GW5909:
+ break;
+ default:
+ return 0;
+ }
+
return i2c_set_bus_num(dev->bus) == 0 &&
i2c_probe(dev->addr) == 0;
}
static void enable_lvds(struct display_info_t const *dev)
{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
writel(reg, &iomux->gpr[2]);
- /* Enable Backlight */
- gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+ /* Configure GPIO */
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ if (!strncmp(dev->mode.name, "Hannstar", 8)) {
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_request(IMX_GPIO_NR(1, 10), "cabc");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+ } else if (!strncmp(dev->mode.name, "DLC", 3)) {
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Configure backlight */
gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
.bus = 2,
.addr = 0x4,
.pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
+ .detect = detect_lvds,
.enable = enable_lvds,
.mode = {
.name = "Hannstar-XGA",
/* DLC700JMG-T-4 */
.bus = 2,
.addr = 0x38,
- .detect = NULL,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC0700XDP21LF-C-1 */
- .bus = 0,
- .addr = 0,
- .detect = NULL,
+ .bus = 2,
+ .addr = 0x38,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
/* DLC800FIG-T-3 */
.bus = 2,
.addr = 0x14,
- .detect = NULL,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
} }, {
.bus = 2,
.addr = 0x5d,
- .detect = detect_i2c,
+ .detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
-
- /* LVDS Backlight GPIO on LVDS connector - output low */
- SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
#endif
/*
+ * remove reset gpio control as we configure the PHY registers
+ * for internal delay, LED config, and clock config in the bootloader
+ */
+ i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
+ if (i)
+ fdt_delprop(blob, i, "phy-reset-gpios");
+
+ /*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
}
+ /* Display hwmon */
+ gsc_hwmon();
+
return 0;
}
led_default_state();
/* Set board serial/model */
- env_set_ulong("serial#", gsc_get_serial());
+ if (!env_get("serial#"))
+ env_set_ulong("serial#", gsc_get_serial());
env_set("model", gsc_get_model());
/* Set fdt_file vars */
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ int off;
+
/* set board model dt prop */
fdt_setprop_string(blob, 0, "board", gsc_get_model());
+ /* update temp thresholds */
+ off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
+ if (off >= 0) {
+ int minc, maxc, prop;
+
+ get_cpu_temp_grade(&minc, &maxc);
+ fdt_for_each_subnode(prop, blob, off) {
+ const char *type = fdt_getprop(blob, prop, "type", NULL);
+
+ if (type && (!strcmp("critical", type)))
+ fdt_setprop_u32(blob, prop, "temperature", maxc * 1000);
+ else if (type && (!strcmp("passive", type)))
+ fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000);
+ }
+ }
+
return 0;
}
--- /dev/null
+if TARGET_KONTRON_MX6UL
+
+config SYS_BOARD
+ string
+ default "sl-mx6ul"
+
+config SYS_VENDOR
+ string
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ string
+ default "kontron-sl-mx6ul"
+
+endif
--- /dev/null
+Kontron SL/BL i.MX6UL/ULL Boards (N63xx/N64xx)
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx6ul-kontron-n6*
+F: arch/arm/dts/imx6ull-kontron-n6*
+F: board/kontron/sl-mx6ul
+F: configs/kontron-sl-mx6ul_defconfig
+F: doc/board/kontron/sl-mx6ul.rst
+F: include/configs/kontron-sl-mx6ul.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2018 Kontron Electronics GmbH
+
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := sl-mx6ul.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <fdt_support.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /*
+ * Overwrite the memory size in the devicetree that is
+ * passed to the kernel with the actual size detected.
+ */
+ return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ enable_qspi_clk(0);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_fec();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <fsl_esdhc_imx.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/errno.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ BOARD_TYPE_KTN_N631X = 1,
+ BOARD_TYPE_KTN_N641X,
+ BOARD_TYPE_MAX
+};
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* RST */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ // This SDHC interface does not use a CD pin
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
+ i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+iomux_v3_cfg_t const ecspi2_pads[] = {
+ MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(4, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+ gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
+ gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
+
+ enable_spi_clk(true, 1);
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+// DDR 256MB (Hynix H5TQ2G63DFR)
+static struct mx6_ddr3_cfg mem_256M_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x01340134,
+ .p0_mprddlctl = 0x40405052,
+ .p0_mpwrdlctl = 0x40404E48,
+};
+
+// DDR 512MB (Hynix H5TQ4G63DFR)
+static struct mx6_ddr3_cfg mem_512M_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0X01440144,
+ .p0_mprddlctl = 0x40405454,
+ .p0_mpwrdlctl = 0x40404E4C,
+};
+
+// Common DDR parameters (256MB and 512MB)
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000028,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_ctlds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_ras = 0x00000028,
+ .dram_cas = 0x00000028,
+ .dram_odt0 = 0x00000028,
+ .dram_odt1 = 0x00000028,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000028,
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_reset = 0x00000028,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 0, /* Refresh cycles at 64KHz */
+ .refr = 1, /* 2 refresh commands per refresh cycle */
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ unsigned int size;
+
+ // DDR RAM connection is always 16 bit wide. Init IOs.
+ mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+
+ // Try to detect the 512MB RAM chip first.
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
+
+ // Get the available RAM size
+ size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
+
+ gd->ram_size = size;
+
+ if (size == SZ_512M) {
+ // 512MB RAM was detected
+ return;
+ } else if (size == SZ_256M) {
+ // 256MB RAM was detected, use correct config and calibration
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
+ } else {
+ printf("Invalid DDR RAM size detected: %x\n", size);
+ }
+}
+
+static int do_board_detect(void)
+{
+ if (is_mx6ul())
+ gd->board_type = BOARD_TYPE_KTN_N631X;
+ else if (is_mx6ull())
+ gd->board_type = BOARD_TYPE_KTN_N641X;
+
+ printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
+ is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* iomux and setup of UART and SPI */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Detect the board type */
+ do_board_detect();
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC1) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_spi();
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
+ !strcmp(name, "imx6ul-kontron-n631x-s"))
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
+ !strcmp(name, "imx6ull-kontron-n641x-s"))
+ return 0;
+
+ return -1;
+}
--- /dev/null
+if TARGET_KONTRON_MX8MM
+
+config SYS_BOARD
+ string
+ default "sl-mx8mm"
+
+config SYS_VENDOR
+ string
+ default "kontron"
+
+config SYS_CONFIG_NAME
+ string
+ default "kontron-sl-mx8mm"
+
+endif
--- /dev/null
+Kontron SL/BL i.MX8M Mini Boards (N801x)
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx8mm-kontron-n801x-*
+F: board/kontron/sl-mx8mm
+F: configs/kontron-sl-mx8mm_defconfig
+F: doc/board/kontron/sl-mx8mm.rst
+F: include/configs/kontron-sl-mx8mm.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2019 Kontron Electronics GmbH
+
+obj-y := sl-mx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x7E1000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa3080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b0087},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x1},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x17},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
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+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+ if (ddr_size == 4) {
+ *size = 0x100000000;
+ } else if (ddr_size == 3) {
+ *size = 0xc0000000;
+ } else if (ddr_size == 2) {
+ *size = 0x80000000;
+ } else if (ddr_size == 1) {
+ *size = 0x40000000;
+ } else {
+ printf("Unknown DDR type!!!\n");
+ *size = 0x40000000;
+ }
+
+ return 0;
+}
+
+/*
+ * If the SoM is mounted on a baseboard with a USB ethernet controller,
+ * there might be an additional MAC address programmed to the MAC OTP fuses.
+ * Although the i.MX8MM has only one MAC, the MAC0, MAC1 and MAC2 registers
+ * in the OTP fuses can still be used to store two separate addresses.
+ * Try to read the secondary address from MAC1 and MAC2 and adjust the
+ * devicetree so Linux can pick up the MAC address.
+ */
+int fdt_set_usb_eth_addr(void *blob)
+{
+ u32 value = readl(OCOTP_BASE_ADDR + 0x660);
+ unsigned char mac[6];
+ int node, ret;
+
+ mac[0] = value >> 24;
+ mac[1] = value >> 16;
+ mac[2] = value >> 8;
+ mac[3] = value;
+
+ value = readl(OCOTP_BASE_ADDR + 0x650);
+ mac[4] = value >> 24;
+ mac[5] = value >> 16;
+
+ node = fdt_path_offset(blob, fdt_get_alias(blob, "ethernet1"));
+ if (node < 0) {
+ /*
+ * There is no node for the USB ethernet in the devicetree. Just skip.
+ */
+ return 0;
+ }
+
+ if (is_zero_ethaddr(mac)) {
+ printf("\nNo MAC address for USB ethernet set in OTP fuses!\n");
+ return 0;
+ }
+
+ if (!is_valid_ethaddr(mac)) {
+ printf("\nInvalid MAC address for USB ethernet set in OTP fuses!\n");
+ return -EINVAL;
+ }
+
+ ret = fdt_setprop(blob, node, "local-mac-address", &mac, 6);
+ if (ret)
+ ret = fdt_setprop(blob, node, "mac-address", &mac, 6);
+
+ if (ret)
+ printf("\nMissing mac-address or local-mac-address property in dt, skip setting MAC address for USB ethernet\n");
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret = fdt_set_usb_eth_addr(blob);
+
+ if (ret)
+ return ret;
+
+ return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
+}
+
+int board_init(void)
+{
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <i2c.h>
+#include <init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ BOARD_TYPE_KTN_N801X,
+ BOARD_TYPE_KTN_N801X_LVDS,
+ BOARD_TYPE_MAX
+};
+
+#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
+
+static iomux_v3_cfg_t const i2c1_pads[] = {
+ IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
+ IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
+};
+
+static iomux_v3_cfg_t const i2c2_pads[] = {
+ IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
+ IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
+};
+
+static iomux_v3_cfg_t const touch_gpio[] = {
+ IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+bool check_ram_available(long size)
+{
+ long sz = get_ram_size((long *)PHYS_SDRAM, size);
+
+ if (sz == size)
+ return true;
+
+ return false;
+}
+
+static void spl_dram_init(void)
+{
+ u32 size = 0;
+
+ /*
+ * Try the default DDR settings in lpddr4_timing.c to
+ * comply with the Micron 4GB DDR.
+ */
+ if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) {
+ size = 4;
+ } else {
+ /*
+ * Overwrite some values to comply with the Micron 1GB/2GB DDRs.
+ */
+ dram_timing.ddrc_cfg[2].val = 0xa1080020;
+ dram_timing.ddrc_cfg[37].val = 0x1f;
+
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
+
+ if (!ddr_init(&dram_timing)) {
+ if (check_ram_available(SZ_2G))
+ size = 2;
+ else if (check_ram_available(SZ_1G))
+ size = 1;
+ }
+ }
+
+ if (size == 0) {
+ printf("Failed to initialize DDR RAM!\n");
+ size = 1;
+ }
+
+ printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
+ writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+static void touch_reset(void)
+{
+ /*
+ * Toggle the reset of the touch panel.
+ */
+ imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
+
+ gpio_request(TOUCH_RESET_GPIO, "touch_reset");
+ gpio_direction_output(TOUCH_RESET_GPIO, 0);
+ mdelay(20);
+ gpio_direction_output(TOUCH_RESET_GPIO, 1);
+ mdelay(20);
+}
+
+static int i2c_detect(u8 bus, u16 addr)
+{
+ struct udevice *udev;
+ int ret;
+
+ /*
+ * Try to probe the touch controller to check if an LVDS panel is
+ * connected.
+ */
+ ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
+ if (ret == 0)
+ return 0;
+
+ return 1;
+}
+
+int do_board_detect(void)
+{
+ bool lvds = false;
+
+ /*
+ * Check the I2C touch controller to detect a LVDS panel.
+ */
+ imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
+ touch_reset();
+
+ if (i2c_detect(1, 0x5d) == 0) {
+ printf("Touch controller detected, assuming LVDS panel...\n");
+ lvds = true;
+ }
+
+ /*
+ * Check the I2C PMIC to detect the deprecated SoM with DA9063.
+ */
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+
+ if (i2c_detect(0, 0x58) == 0) {
+ printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
+ printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
+ printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
+ }
+
+ if (lvds)
+ gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
+ else
+ gd->board_type = BOARD_TYPE_KTN_N801X;
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
+ !strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
+ !strncmp(name, "imx8mm-kontron-n801x-s", 22))
+ return 0;
+
+ return -1;
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ puts("Normal Boot\n");
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0)
+ printf("Failed to find clock node. Check device tree\n");
+}
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret = pmic_get("pmic@25", &dev);
+
+ if (ret == -ENODEV)
+ puts("No pmic found\n");
+
+ if (ret)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* increase VDD_DRAM to 0.95V for 1.5GHz DDR */
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
+
+ /* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
+ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* PMIC initialization */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Detect the board type */
+ do_board_detect();
+
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC2) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
int board_late_init(void)
{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(NULL);
+#endif
+
#if defined(CONFIG_VIDEO_IPUV3)
struct udevice *dev;
int xpos, ypos, ret;
ROM_VERSION v2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x920000
+LOADER u-boot-spl-ddr.bin 0x920000
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(void)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 2,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
break;
};
udelay(100);
+ spl_dram_perform_cal();
}
void board_init_f(ulong dummy)
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(u8 dsize)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = dsize,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
+ u8 dsize = 2;
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL:
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
};
udelay(100);
+ spl_dram_perform_cal(dsize);
}
static iomux_v3_cfg_t const gpio_reset_pad[] = {
return buf;
}
+__weak void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ return spl_get_fit_load_buffer(sectors * bl_len);
+}
+
/*
* Weak default function to allow customizing SPL fit loading for load-only
* use cases by allowing to skip the parsing/processing of the FIT contents
return false;
}
+/*
+ * Weak default function to allow fixes after fit header
+ * is loaded.
+ */
+__weak void *spl_load_simple_fit_fix_load(const void *fit)
+{
+ return (void *)fit;
+}
+
static void warn_deprecated(const char *msg)
{
printf("DEPRECATED: %s\n", msg);
* For FIT with external data, data is not loaded in this step.
*/
sectors = get_aligned_image_size(info, size, 0);
- buf = spl_get_fit_load_buffer(sectors * info->bl_len);
+ buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
count = info->read(info, sector, sectors, buf);
ctx->fit = buf;
if (spl_load_simple_fit_skip_processing())
return 0;
+ ctx.fit = spl_load_simple_fit_fix_load(ctx.fit);
+
ret = spl_simple_fit_parse(&ctx);
if (ret < 0)
return ret;
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6Q=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_IMX_CONFIG="board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ABX80X=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_DM_THERMAL=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_TPM2_FTPM_TEE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPM=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_SECURE_BOOT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_KONTRON_MX6UL=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-n631x-s"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx6ul-kontron-n631x-s imx6ull-kontron-n641x-s"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=2
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=10000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=4
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x1f0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_KONTRON_MX8MM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg"
+CONFIG_BOARD_TYPES=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_SF=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_MACRONIX=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MSCC=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_CONS_INDEX=2
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_IMX_WATCHDOG=y
+# CONFIG_HEXDUMP is not set
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x71000000
CONFIG_SPL_GPIO=y
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
-# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x70800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi"
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
CONFIG_TARGET_SMEGW01=y
+CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
+CONFIG_DM_ETH=y
:maxdepth: 2
sl28
+ sl-mx6ul
+ sl-mx8mm
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron Electronics SL i.MX6UL/ULL SoM
+======================================
+
+The Kontron SoM-Line i.MX6UL/ULL (N6x1x) by Kontron Electronics GmbH is a SoM module
+with either an i.MX6UL or i.MX6ULL SoC, 256/512 MB DDR3 RAM, SPI NOR, SPI NAND and Ethernet PHY.
+
+The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
+RGB, SD card, CAN, RS485, RS232 and much more.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron-sl-mx6ul_defconfig
+ $ make
+
+Burn the flash.bin to SD card at an offset of 1 KiB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
+
+Further Information
+-------------------
+
+The bootloader configuration is setup to be used with kernel FIT images. Legacy
+images might not be working out of the box.
+
+Please see https://docs.kontron-electronics.de for further vendor documentation.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron Electronics SL i.MX8MM SoM
+==================================
+
+The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module
+with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
+
+The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
+HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
+
+Quick Start
+-----------
+
+- Get and Build the Trusted Firmware-A (TF-A)
+- Get the DDR firmware
+- Build U-Boot
+- Boot
+
+Get and Build the Trusted Firmware-A (TF-A)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
+There are two sources for the TF-A. Mainline and NXP. Get the one you prefer
+(support and features might differ).
+
+**NXP's imx-atf**
+
+1. Get TF-A from: https://source.codeaurora.org/external/imx/imx-atf, branch: imx_5.4.70_2.3.0
+2. Apply the patch to select the correct UART for the console, otherwise the TF-A will lock up during boot.
+3. Build
+
+ .. code-block:: bash
+
+ $ make PLAT=imx8mm bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+**Mainline TF-A**
+
+1. Get TF-A from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/, tag: v2.4
+2. Build
+
+ .. code-block:: bash
+
+ $ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- IMX_BOOT_UART_BASE="0x30880000" bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the DDR firmware
+^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+ $ chmod +x firmware-imx-8.9.bin
+ $ ./firmware-imx-8.9.bin
+ $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make kontron-sl-mx8mm_defconfig
+ $ export ATF_LOAD_ADDR=0x920000
+ $ make
+
+Burn the flash.bin to SD card at an offset of 33 KiB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 conv=notrunc
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
+
+Further Information
+-------------------
+
+The bootloader configuration is setup to be used with kernel FIT images. Legacy
+images might not be working out of the box.
+
+Please see https://docs.kontron-electronics.de for further vendor documentation.
.. code-block:: bash
$sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
- $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync
Boot
----
Programmable memory pages that are stored on the some
Freescale i.MX processors.
+config SPL_MXC_OCOTP
+ bool "Enable MXC OCOTP driver in SPL"
+ depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+ default y
+ help
+ If you say Y here, you will get support for the One Time
+ Programmable memory pages, that are stored on some
+ Freescale i.MX processors, in SPL.
+
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
-obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
+ /* clear the reset bit on strobe dll before any setting */
+ esdhc_write32(®s->strobe_dllctrl, 0);
/*
* enable strobe dll ctrl and adjust the delay target
* for the uSDHC loopback read clock
*/
val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
(priv->strobe_dll_delay_target <<
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
esdhc_write32(®s->strobe_dllctrl, val);
- /* wait 1us to make sure strobe dll status register stable */
- mdelay(1);
+ /* wait 5us to make sure strobe dll status register stable */
+ mdelay(5);
val = esdhc_read32(®s->strobe_dllstat);
if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
pr_warn("HS400 strobe DLL status REF not lock!\n");
if (priv->clock != clock)
set_sysctl(priv, mmc, clock);
-#ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
#endif
}
+#ifdef MMC_SUPPORTS_TUNING
/*
* For HS400/HS400ES mode, make sure set the strobe dll in the
* target clock rate. So call esdhc_set_strobe_dll() after the
| ESDHC_FLAG_HS400,
};
+static struct esdhc_soc_data usdhc_imx7ulp_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+};
+
static struct esdhc_soc_data usdhc_imx8qm_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
{ .compatible = "fsl,imx6sl-usdhc", },
{ .compatible = "fsl,imx6q-usdhc", },
{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
- { .compatible = "fsl,imx7ulp-usdhc", },
+ { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,},
{ .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
imply CMD_NAND
help
This enables the NAND driver for the NAND flash controller on the
- i.MX27 / i.MX31 / i.MX5 rocessors.
+ i.MX27 / i.MX31 / i.MX5 processors.
config NAND_MXS
bool "MXS NAND support"
void nand_deselect(void)
{
}
+
+u32 nand_spl_adjust_offset(u32 sector, u32 offs)
+{
+ /* Handle the offset adjust in nand_spl_load_image,*/
+ return offs;
+}
static const struct udevice_id rv8803_rtc_ids[] = {
{ .compatible = "microcrystal,rv8803", },
+ { .compatible = "epson,rx8803" },
+ { .compatible = "epson,rx8900" },
{ }
};
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"bootdevs=usb mmc sata flash\0" \
* - Set the stack at the end of the free area section, at 0x00946BB8.
* - The BOOT ROM loads what they consider the firmware image
* which consists of a 4K header in front of us that contains the IVT, DCD
- * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
- * 64KB is more then enough for the SPL.
+ * and some padding. However, the manual also states that the ROM uses the
+ * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use
+ * this range for stack and malloc, the SPL itself must fit below 0x920000,
+ * or the image will be truncated in at least some boot modes like USB SDP.
+ * Thus our max size is really 0x00920000 - 0x00912000. If necessary,
+ * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space
+ * for the SPL, but 56KB should be more than enough for the SPL.
*/
-#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0xE000
#define CONFIG_SPL_STACK 0x00946BB8
/*
- * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
- * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
- * boot media (given that boot media specific offset is configured properly).
+ * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding)
+ * The extra padding could be removed, but this value was used historically
+ * based on an incorrect CONFIG_SPL_MAX_SIZE definition.
+ * This allows to write the SPL/U-Boot combination generated with
+ * u-boot-with-spl.imx directly to a boot media (given that boot media specific
+ * offset is configured properly).
*/
#define CONFIG_SPL_PAD_TO 0x11000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
+#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
+
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ *
+ * Configuration settings for the Kontron i.MX6UL boards/SoMs.
+ */
+#ifndef __KONTRON_MX6UL_CONFIG_H
+#define __KONTRON_MX6UL_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#include "mx6_common.h"
+#ifdef CONFIG_SPL_BUILD
+#include "imx6_spl.h"
+#endif
+
+/* RAM */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+
+/* Board and environment settings */
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_HOSTNAME "kontron-mx6ul"
+#define CONFIG_ETHPRIME "eth0"
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+/* Boot order for distro boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(UBIFS, ubifs, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80100000\0" \
+ "bootdelay=3\0" \
+ "ethact=" CONFIG_ETHPRIME "\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ BOOTENV
+
+#endif /* __KONTRON_MX6UL_CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ *
+ * Configuration settings for the Kontron SL/BL i.MX8M-Mini boards and modules (N81xx).
+ */
+#ifndef __KONTRON_MX8MM_CONFIG_H
+#define __KONTRON_MX8MM_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#ifdef CONFIG_SPL_BUILD
+#include <config.h>
+#endif
+
+/* RAM */
+#define PHYS_SDRAM DDR_CSD1_BASE_ADDR
+#define PHYS_SDRAM_SIZE (SZ_4G)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Board and environment settings */
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+#define CONFIG_HOSTNAME "kontron-mx8mm"
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na)
+#include <config_distro_bootcmd.h>
+/* Do not try to probe USB net adapters for net boot */
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START
+#else
+#define BOOTENV
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
+#define CONFIG_FSL_USDHC
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x91fff0
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x930000
+#endif
+
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x44000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "pxefile_addr_r=0x46000000\0" \
+ "scriptaddr=0x46000000\0" \
+ "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
+ "bootdelay=3\0" \
+ "hostname=" CONFIG_HOSTNAME "\0" \
+ BOOTENV
+
+#endif /* __KONTRON_MX8MM_CONFIG_H */
"splashfile=boot/usplash.bmp.gz\0" \
"splashimage=0x88000000\0" \
"splashpos=m,m\0" \
+ "altbootcmd=" \
+ "if test ${mmcpart} -eq 1 ; then " \
+ "setenv mmcpart 2 ; " \
+ "else " \
+ "setenv mmcpart 1 ; " \
+ "fi ; " \
+ "boot\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"addcons=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc addmtd\0" \
"mmcload=" \
- "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
- "${kernel_addr_r} ${bootfile}\0" \
+ "mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \
+ "${kernel_addr_r} ${bootfile} || reset\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
"rootwait\0" \
"mmc_mmc=" \
- "run mmcload mmcargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
+ "run mmcload mmcargs addargs || reset ; " \
+ "bootm ${kernel_addr_r} ; reset\0" \
"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
"net_nfs=" \
"run netload nfsargs addip addargs ; " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
-
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
"bootm_size=0x10000000\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
#define ESDHC_STROBE_DLL_STATUS 0x74
#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
bool spl_load_simple_fit_skip_processing(void);
/**
+ * spl_load_simple_fit_fix_load() - Hook to make fixes
+ * after fit image header is loaded
+ *
+ * Returns pointer to fit
+ */
+void *spl_load_simple_fit_fix_load(const void *fit);
+
+/**
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
config RSA
bool "Use RSA Library"
- select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
help
RSA support. This enables the RSA algorithm used for FIT image
config RSA_FREESCALE_EXP
bool "Enable RSA Modular Exponentiation with FSL crypto accelerator"
- depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
+ depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
help
Enables driver for RSA modular exponentiation using Freescale cryptographic
accelerator - CAAM.
from patman import terminal
from patman.terminal import Print
+# This indicates an new int or hex Kconfig property with no default
+# It hangs the build since the 'conf' tool cannot proceed without valid input.
+#
+# We get a repeat sequence of something like this:
+# >>
+# Break things (BREAK_ME) [] (NEW)
+# Error in reading or end of file.
+# <<
+# which indicates that BREAK_ME has an empty default
+RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)')
+
"""
Theory of Operation
_working_dir: Base working directory containing all threads
_single_builder: BuilderThread object for the singer builder, if
threading is not being used
+ _terminated: Thread was terminated due to an error
+ _restarting_config: True if 'Restart config' is detected in output
"""
class Outcome:
"""Records a build outcome for a single make invocation
self.work_in_output = work_in_output
if not self.squash_config_y:
self.config_filenames += EXTRA_CONFIG_FILENAMES
+ self._terminated = False
+ self._restarting_config = False
self.warnings_as_errors = warnings_as_errors
self.col = terminal.Color()
args: Arguments to pass to make
kwargs: Arguments to pass to command.RunPipe()
"""
+
+ def check_output(stream, data):
+ if b'Restart config' in data:
+ self._restarting_config = True
+
+ # If we see 'Restart config' following by multiple errors
+ if self._restarting_config:
+ m = RE_NO_DEFAULT.findall(data)
+
+ # Number of occurences of each Kconfig item
+ multiple = [m.count(val) for val in set(m)]
+
+ # If any of them occur more than once, we have a loop
+ if [val for val in multiple if val > 1]:
+ self._terminated = True
+ return True
+ return False
+
+ self._restarting_config = False
+ self._terminated = False
cmd = [self.gnu_make] + list(args)
result = command.RunPipe([cmd], capture=True, capture_stderr=True,
- cwd=cwd, raise_on_error=False, infile='/dev/null', **kwargs)
+ cwd=cwd, raise_on_error=False, infile='/dev/null',
+ output_func=check_output, **kwargs)
+
+ if self._terminated:
+ # Try to be helpful
+ result.stderr += '(** did you define an int/hex Kconfig with no default? **)'
+
if self.verbose_build:
result.stdout = '%s\n' % (' '.join(cmd)) + result.stdout
result.combined = '%s\n' % (' '.join(cmd)) + result.combined
work_in_output: Use the output directory as the work directory and
don't write to a separate output directory.
"""
- # Fatal error
- if result.return_code < 0:
- return
-
# If we think this might have been aborted with Ctrl-C, record the
# failure but not that we are 'done' with this board. A retry may fix
# it.
- maybe_aborted = result.stderr and 'No child processes' in result.stderr
+ maybe_aborted = result.stderr and 'No child processes' in result.stderr
- if result.already_done:
+ if result.return_code >= 0 and result.already_done:
return
# Write the output and stderr
elif os.path.exists(errfile):
os.remove(errfile)
+ # Fatal error
+ if result.return_code < 0:
+ return
+
if result.toolchain:
# Write the build result and toolchain information.
done_file = self.builder.GetDoneFile(result.commit_upto,
if (ptr == MAP_FAILED) {
fprintf(stderr, "Can't read %s: %s\n",
datafile, strerror(errno));
- exit(EXIT_FAILURE);
+ goto err_mmap;
}
size = sbuf.st_size - datafile_offset;
}
munmap((void *)ptr, sbuf.st_size);
+err_mmap:
close(dfd);
}
def RunPipe(pipe_list, infile=None, outfile=None,
capture=False, capture_stderr=False, oneline=False,
- raise_on_error=True, cwd=None, binary=False, **kwargs):
+ raise_on_error=True, cwd=None, binary=False,
+ output_func=None, **kwargs):
"""
Perform a command pipeline, with optional input/output filenames.
capture: True to capture output
capture_stderr: True to capture stderr
oneline: True to strip newline chars from output
+ output_func: Output function to call with each output fragment
+ (if it returns True the function terminates)
kwargs: Additional keyword arguments to cros_subprocess.Popen()
Returns:
CommandResult object
if capture:
result.stdout, result.stderr, result.combined = (
- last_pipe.CommunicateFilter(None))
+ last_pipe.CommunicateFilter(output_func))
if result.stdout and oneline:
result.output = result.stdout.rstrip(b'\r\n')
result.return_code = last_pipe.wait()
sys.stdout or sys.stderr.
data: a string containing the data
+ Returns:
+ True to terminate the process
+
Note: The data read is buffered in memory, so do not use this
method if the data size is large or unlimited.
stderr = bytearray()
combined = bytearray()
+ stop_now = False
input_offset = 0
while read_set or write_set:
try:
stdout += data
combined += data
if output:
- output(sys.stdout, data)
+ stop_now = output(sys.stdout, data)
if self.stderr in rlist:
data = b''
# We will get an error on read if the pty is closed
stderr += data
combined += data
if output:
- output(sys.stderr, data)
+ stop_now = output(sys.stderr, data)
+ if stop_now:
+ self.terminate()
# All data exchanged. Translate lists into strings.
stdout = self.ConvertData(stdout)
projects / platform / kernel / u-boot.git / commitdiff