drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0

Set the DP 2.0 128b/132b channel encoding for UHBR rates.

v2: Fix UHBR port clock check, use intel_dp_is_uhbr()

Bspec: 54128
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c88b08d80a96d1229ae941b296590633be4d8711.1631191763.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cb8f303265a741b845980440741579ed121c5026..91ee32ffba97a288ca11fec02ad17a04d725068b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -408,6 +408,20 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
                return master_transcoder + 1;
 }
 
+static void
+intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state)
+{
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+       u32 val = 0;
+
+       if (intel_dp_is_uhbr(crtc_state))
+               val = TRANS_DP2_128B132B_CHANNEL_CODING;
+
+       intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
+}
+
 /*
  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
  *
@@ -2376,7 +2390,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
         */
        intel_ddi_enable_pipe_clock(encoder, crtc_state);
 
-       /* 5.b Not relevant to i915 for now */
+       /* 5.b Configure transcoder for DP 2.0 128b/132b */
+       intel_ddi_config_transcoder_dp2(encoder, crtc_state);
 
        /*
         * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST