irqchip/hip04: Report that effective affinity is a single target
authorMarc Zyngier <marc.zyngier@arm.com>
Fri, 18 Aug 2017 08:39:23 +0000 (09:39 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Fri, 18 Aug 2017 08:54:42 +0000 (10:54 +0200)
The HIP04 driver only targets a single CPU at a time, even if
the notional affinity is wider. Let's inform the core code
about this.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: http://lkml.kernel.org/r/20170818083925.10108-11-marc.zyngier@arm.com
arch/arm/mach-hisi/Kconfig
drivers/irqchip/irq-hip04.c

index a3b091a..65a048f 100644 (file)
@@ -39,6 +39,7 @@ config ARCH_HIP04
        select HAVE_ARM_ARCH_TIMER
        select MCPM if SMP
        select MCPM_QUAD_CLUSTER if SMP
+       select GENERIC_IRQ_EFFECTIVE_AFF_MASK
        help
          Support for Hisilicon HiP04 SoC family
 
index c1b4ee9..5b4fd2f 100644 (file)
@@ -165,6 +165,8 @@ static int hip04_irq_set_affinity(struct irq_data *d,
        writel_relaxed(val | bit, reg);
        raw_spin_unlock(&irq_controller_lock);
 
+       irq_data_update_effective_affinity(d, cpumask_of(cpu));
+
        return IRQ_SET_MASK_OK;
 }
 #endif
@@ -312,6 +314,7 @@ static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
                irq_set_chip_and_handler(irq, &hip04_irq_chip,
                                         handle_fasteoi_irq);
                irq_set_probe(irq);
+               irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
        }
        irq_set_chip_data(irq, d->host_data);
        return 0;