#endif // _TARGET_X86_
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS && defined(_TARGET_XARCH_)
+#if defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_)
void genHWIntrinsic(GenTreeHWIntrinsic* node);
void genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins);
void genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins);
void genLZCNTIntrinsic(GenTreeHWIntrinsic* node);
void genPCLMULQDQIntrinsic(GenTreeHWIntrinsic* node);
void genPOPCNTIntrinsic(GenTreeHWIntrinsic* node);
-#endif // FEATURE_HW_INTRINSICS
+#endif // defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_)
#if !defined(_TARGET_64BIT_)
break;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
genHWIntrinsic(treeNode->AsHWIntrinsic());
break;
SIMDVector3Handle = nullptr;
SIMDVector4Handle = nullptr;
SIMDVectorHandle = nullptr;
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
#if defined(_TARGET_ARM64_)
Vector64FloatHandle = nullptr;
Vector64DoubleHandle = nullptr;
void SetOpLclRelatedToSIMDIntrinsic(GenTreePtr op);
#endif
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
NamedIntrinsic hwIntrinsicID,
var_types baseType,
bool tailCall);
NamedIntrinsic lookupNamedIntrinsic(CORINFO_METHOD_HANDLE method);
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
static InstructionSet lookupHWIntrinsicISA(const char* className);
static NamedIntrinsic lookupHWIntrinsic(const char* methodName, InstructionSet isa);
static InstructionSet isaOfHWIntrinsic(NamedIntrinsic intrinsic);
CORINFO_CLASS_HANDLE SIMDVector4Handle;
CORINFO_CLASS_HANDLE SIMDVectorHandle;
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
#if defined(_TARGET_ARM64_)
CORINFO_CLASS_HANDLE Vector64FloatHandle;
CORINFO_CLASS_HANDLE Vector64DoubleHandle;
// AVX2: 32-byte Vector<T> and Vector256<T>
unsigned int maxSIMDStructBytes()
{
-#if FEATURE_HW_INTRINSICS && defined(_TARGET_XARCH_)
+#if defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_)
if (compSupports(InstructionSet_AVX))
{
return YMM_REGSIZE_BYTES;
return;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
if ((this->AsHWIntrinsic()->gtOp1 != nullptr) && this->AsHWIntrinsic()->gtOp1->OperIsList())
{
if ((ins != INS_movsx) && // These three instructions support high register
(ins != INS_movzx) // encodings for reg1
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
&& (ins != INS_crc32)
#endif
)
emitCurIGsize += sz;
}
-#ifdef DEBUG
-static bool isAvxBlendv(instruction ins)
-{
- return ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb;
-}
-
-static bool isSse41Blendv(instruction ins)
-{
- return ins == INS_blendvps || ins == INS_blendvpd || ins == INS_pblendvb;
-}
-#endif
+#ifndef LEGACY_BACKEND
void emitter::emitIns_R_R_R_R(
instruction ins, emitAttr attr, regNumber targetReg, regNumber reg1, regNumber reg2, regNumber reg3)
emitCurIGsize += sz;
}
+#endif // !LEGACY_BACKEND
+
/*****************************************************************************
*
* Add an instruction with a register + static member operands.
emitAdjustStackDepthPushPop(ins);
}
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
void emitter::emitIns_SIMD_R_R_A(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, GenTreeIndir* indir)
{
if (UseVEXEncoding())
// INS_bt operands are reversed. Display them in the normal order.
printf("%s, %s", emitRegName(id->idReg2(), attr), emitRegName(id->idReg1(), attr));
}
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
else if (ins == INS_crc32 && attr != EA_8BYTE)
{
printf("%s, %s", emitRegName(id->idReg1(), EA_4BYTE), emitRegName(id->idReg2(), attr));
#endif // _TARGET_AMD64_
}
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
else if ((ins == INS_crc32) || (ins == INS_lzcnt) || (ins == INS_popcnt))
{
code = insEncodeRMreg(ins, code);
return (IsDstDstSrcAVXInstruction(ins) || IsDstSrcSrcAVXInstruction(ins));
}
bool Is4ByteAVXInstruction(instruction ins);
+bool isAvxBlendv(instruction ins)
+{
+ return ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb;
+}
+bool isSse41Blendv(instruction ins)
+{
+ return ins == INS_blendvps || ins == INS_blendvpd || ins == INS_pblendvb;
+}
#else // LEGACY_BACKEND
bool UseVEXEncoding()
{
{
return false;
}
+bool isAvxBlendv(instruction ins)
+{
+ return false;
+}
+bool isSse41Blendv(instruction ins)
+{
+ return false;
+}
bool TakesVexPrefix(instruction ins)
{
return false;
void emitIns_R_R_S_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int varx, int offs, int ival);
+#ifndef LEGACY_BACKEND
void emitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4);
+#endif // !LEGACY_BACKEND
void emitIns_S(instruction ins, emitAttr attr, int varx, int offs);
void emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp);
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
void emitIns_SIMD_R_R_AR(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber base);
void emitIns_SIMD_R_R_A_I(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, GenTreeIndir* indir, int ival);
void emitIns_SIMD_R_R_C_I(
void emitIns_SIMD_R_R_R(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber reg2);
void emitIns_SIMD_R_R_R_R(
instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber reg2, regNumber reg3);
-#endif
+#endif // FEATURE_HW_INTRINSICS
#if FEATURE_STACK_FP_X87
void emitIns_F_F0(instruction ins, unsigned fpreg);
break;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
if ((op1->AsHWIntrinsic()->gtHWIntrinsicId != op2->AsHWIntrinsic()->gtHWIntrinsicId) ||
(op1->AsHWIntrinsic()->gtSIMDBaseType != op2->AsHWIntrinsic()->gtSIMDBaseType) ||
break;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
hash += tree->gtHWIntrinsic.gtHWIntrinsicId;
hash += tree->gtHWIntrinsic.gtSIMDBaseType;
break;
#endif
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
{
GenTreeHWIntrinsic* hwintrinsicOp = tree->AsHWIntrinsic();
return;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
if (m_node->AsHWIntrinsic()->gtOp1 == nullptr)
{
};
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
extern const char* getHWIntrinsicName(NamedIntrinsic intrinsic);
#endif // FEATURE_HW_INTRINSICS
}
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
if (tree->gtOper == GT_HWIntrinsic)
{
printf(" %s %s",
structHnd = gtGetStructHandleForSIMD(tree->gtType, tree->AsSIMD()->gtSIMDBaseType);
break;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
structHnd = gtGetStructHandleForHWSIMD(tree->gtType, tree->AsHWIntrinsic()->gtSIMDBaseType);
break;
}
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
GenTreeHWIntrinsic* Compiler::gtNewSimdHWIntrinsicNode(var_types type,
NamedIntrinsic hwIntrinsicID,
var_types baseType,
return OperIsSIMD(gtOper);
}
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
inline bool OperIsSimdHWIntrinsic() const;
#else
inline bool OperIsSimdHWIntrinsic() const
case GT_LEA:
case GT_RETFILT:
case GT_NOP:
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
#endif // FEATURE_HW_INTRINSICS
return true;
case GT_SIMD:
#endif // !FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
#endif // FEATURE_HW_INTRINSICS
};
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
struct GenTreeHWIntrinsic : public GenTreeJitIntrinsic
{
NamedIntrinsic gtHWIntrinsicId;
GTNODE(SIMD , GenTreeSIMD ,0,GTK_BINOP|GTK_EXOP) // SIMD functions/operators/intrinsics
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
GTNODE(HWIntrinsic , GenTreeHWIntrinsic ,0,GTK_BINOP|GTK_EXOP) // hardware intrinsics
#endif // FEATURE_HW_INTRINSICS
#ifdef FEATURE_SIMD
GTSTRUCT_1(SIMD , GT_SIMD)
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
GTSTRUCT_1(HWIntrinsic , GT_HWIntrinsic)
#endif // FEATURE_HW_INTRINSICS
GTSTRUCT_1(AllocObj , GT_ALLOCOBJ)
assert(varTypeIsSIMD(structVal) && (structVal->gtType == structType));
break;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
assert(varTypeIsSIMD(structVal) && (structVal->gtType == structType));
break;
}
else
#endif
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
if (blockNode->OperGet() == GT_HWIntrinsic && blockNode->AsHWIntrinsic()->isSIMD())
{
parent->gtOp.gtOp2 = impNormStructVal(blockNode, structHnd, curLevel, forceNormalization);
{
ni = lookupNamedIntrinsic(method);
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
#ifdef _TARGET_XARCH_
if (ni > NI_HW_INTRINSIC_START && ni < NI_HW_INTRINSIC_END)
{
}
}
-#if FEATURE_HW_INTRINSICS && defined(_TARGET_XARCH_)
+#if defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_)
if ((namespaceName != nullptr) && strcmp(namespaceName, "System.Runtime.Intrinsics.X86") == 0)
{
InstructionSet isa = lookupHWIntrinsicISA(className);
result = lookupHWIntrinsic(methodName, isa);
}
-#endif // FEATURE_HW_INTRINSICS
+#endif // defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_)
return result;
}
void TreeNodeInfoInitSIMD(GenTreeSIMD* tree, TreeNodeInfo* info);
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
void TreeNodeInfoInitHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, TreeNodeInfo* info);
#endif // FEATURE_HW_INTRINSICS
break;
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
TreeNodeInfoInitHWIntrinsic(tree->AsHWIntrinsic(), info);
break;
}
#endif // FEATURE_SIMD
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
//------------------------------------------------------------------------
// TreeNodeInfoInitHWIntrinsic: Set the NodeInfo for a GT_HWIntrinsic tree.
//
setUsesSIMDTypes(true);
}
}
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
else if (isIntrinsicType(typeHnd))
{
const size_t Vector64SizeBytes = 64 / 8;
}
#endif
-#if FEATURE_HW_INTRINSICS
+#ifdef FEATURE_HW_INTRINSICS
if (oper == GT_HWIntrinsic)
{
// TODO-CQ: For now hardware intrinsics are not handled by value numbering to be amenable for CSE'ing.