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Fix duplicate ChangeLog entries.
authorMartin Liska <mliska@suse.cz>
Wed, 4 Nov 2020 08:42:27 +0000 (09:42 +0100)
committerMartin Liska <mliska@suse.cz>
Wed, 4 Nov 2020 08:42:39 +0000 (09:42 +0100)
gcc/ChangeLog patch | blob | history
gcc/testsuite/ChangeLog patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 40fb654..93d6b0f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -184,16 +184,6 @@
        * config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add
        intrinsics.
 
-2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry.
-       (vbfcvt_high, bfcvt): Likewise.
-       * config/aarch64/aarch64-simd.md(aarch64_vbfcvt<mode>): New entry.
-       (aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise.
-       * config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic.
-       * config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise.
-       (vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise.
-
 2020-11-03  Richard Biener  <rguenther@suse.de>
 
        PR bootstrap/97666
@@ -260,32 +250,6 @@
        Once any outermost loop gets unrolled, flag cfun pending_TODOs
        PENDING_TODO_force_next_scalar_cleanup on.
 
-2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * config/aarch64/aarch64-simd-builtins.def (vget_lo_half): New entry.
-       (vget_hi_half): Likewise.
-       * config/aarch64/aarch64-simd.md (aarch64_vget_lo_halfv8bf): New entry.
-       (aarch64_vget_hi_halfv8bf): Likewise.
-       * config/aarch64/arm_neon.h (vget_low_bf16): New intrinsic.
-       (vget_high_bf16): Likewise.
-
-2020-11-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>
-
-       PR target/97205
-       * cfgexpand.c (align_local_variable): Make SSA_NAMEs
-       at least MODE_ALIGNED.
-       (expand_one_stack_var_at): Increase MEM_ALIGN for SSA_NAMEs.
-
-2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry.
-       (vbfcvt_high, bfcvt): Likewise.
-       * config/aarch64/aarch64-simd.md(aarch64_vbfcvt<mode>): New entry.
-       (aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise.
-       * config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic.
-       * config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise.
-       (vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise.
-
 2020-11-02  Alan Modra  <amodra@gmail.com>
 
        PR middle-end/97267
@@ -2146,29 +2110,6 @@
        (vrp_simplify_cond_using_ranges): Move...
        * tree-vrp.c (vrp_simplify_cond_using_ranges): ...to here.
 
-2020-10-22  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * config/arm/mve.md (mve_vmaxq_<supf><mode>): Replace with ...
-       (mve_vmaxq_s<mode>, mve_vmaxq_u<mode>): ... these new insns to
-       use smax/umax instead of VMAXQ.
-       (mve_vminq_<supf><mode>): Replace with ...
-       (mve_vminq_s<mode>, mve_vminq_u<mode>): ... these new insns to
-       use smin/umin instead of VMINQ.
-       (mve_vmaxnmq_f<mode>): Use smax instead of VMAXNMQ_F.
-       (mve_vminnmq_f<mode>): Use smin instead of VMINNMQ_F.
-       * config/arm/vec-common.md (smin<mode>3): Use the new mode macros
-       ARM_HAVE_<MODE>_ARITH.
-       (umin<mode>3, smax<mode>3, umax<mode>3): Likewise.
-
-2020-10-22  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * config/arm/mve.md (mve_vmulq<mode>): New entry for vmul instruction
-       using expression 'mult'.
-       (mve_vmulq_f<mode>): Use mult instead of VMULQ_F.
-       * config/arm/neon.md (mul<mode>3): Removed.
-       * config/arm/vec-common.md (mul<mode>3): Use the new mode macros
-       ARM_HAVE_<MODE>_ARITH. Use mode iterator VDQWH instead of VALLW.
-
 2020-10-20  Andrew MacLeod  <amacleod@redhat.com>
 
        PR tree-optimization/97505
@@ -4384,10 +4325,6 @@
        * doc/invoke.texi: Add z15/arch13 to the list of documented
        -march/-mtune options.
 
-2020-10-05  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes.
-
 2020-10-05  Aldy Hernandez  <aldyh@redhat.com>
 
        * value-range.cc (irange::legacy_intersect): Only handle
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b3c0b8f..4020022 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -30,7 +30,7 @@
        a superflous target test in the dg-do compile
        directive while at it.
 
-2020-11-03  Dennis Zhang  <denzha01@e124712.cambridge.arm.com>
+2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
 
        * gcc.target/aarch64/advsimd-intrinsics/bf16_get.c: New test.
        * gcc.target/aarch64/advsimd-intrinsics/bf16_get-be.c: New test.
@@ -40,11 +40,6 @@
        PR c++/97632
        * g++.dg/warn/Winit-list4.C: New test.
 
-2020-11-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>
-
-       PR target/97205
-       * gcc.c-torture/compile/pr97205.c: New test.
-
 2020-11-03  Andrea Corallo  <andrea.corallo@arm.com>
 
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_bf16_indices_1.c:
@@ -97,7 +92,7 @@
        * gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
        * gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
 
-2020-11-03  Dennis Zhang  <denzha01@e124712.cambridge.arm.com>
+2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
 
        * gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c
        (test_vcvt_f32_bf16, test_vcvtq_low_f32_bf16): New tests.
@@ -229,22 +224,11 @@
        * gcc.dg/vect/bb-slp-41.c: Likewise.
        * gcc.dg/tree-ssa/pr96789.c: New test.
 
-2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * gcc.target/aarch64/advsimd-intrinsics/bf16_get.c: New test.
-       * gcc.target/aarch64/advsimd-intrinsics/bf16_get-be.c: New test.
-       
 2020-11-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
        PR target/97205
        * gcc.c-torture/compile/pr97205.c: New test.
 
-2020-11-03  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c
-       (test_vcvt_f32_bf16, test_vcvtq_low_f32_bf16): New tests.
-       (test_vcvtq_high_f32_bf16, test_vcvth_f32_bf16): Likewise.
-       
 2020-11-02  Alan Modra  <amodra@gmail.com>
 
        PR middle-end/97267
@@ -1150,7 +1134,7 @@
        * gcc.dg/pr43783.c: ... here.  Add dg-do compile, dg-options and
        dg-error directives.
 
-2020-10-23  Dennis Zhang  <dennis.zh@live.com>
+2020-10-23  Dennis Zhang  <dennis.zhang@arm.com>
 
        * gcc.target/arm/simd/mve-vsub_1.c: New test.
 
@@ -1162,10 +1146,6 @@
        PR middle-end/97521
        * gcc.target/i386/pr97521.c: New testcase.
 
-2020-10-23  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * gcc.target/arm/simd/mve-vsub_1.c: New test.
-
 2020-10-22  Alan Modra  <amodra@gmail.com>
 
        * gcc.target/powerpc/vec-splati-runnable.c: Don't abort on
@@ -1258,15 +1238,11 @@
 
        * gcc.target/i386/pr97249-1.c: New test.
 
-2020-10-22  Dennis Zhang  <dennis.zh@live.com>
-
-       * gcc.target/arm/simd/mve-vminmax_1.c: New test.
-
 2020-10-22  Andrew MacLeod  <amacleod@redhat.com>
 
        * gcc.dg/pr97520.c: New.
 
-2020-10-22  Dennis Zhang  <dennis.zh@live.com>
+2020-10-22  Dennis Zhang  <dennis.zhang@arm.com>
 
        * gcc.target/arm/simd/mve-vmul_1.c: New test.
 
@@ -1399,10 +1375,6 @@
 
        * gcc.target/arm/simd/mve-vminmax_1.c: New test.
 
-2020-10-22  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * gcc.target/arm/simd/mve-vmul_1.c: New test.
-
 2020-10-20  Jeff Law  <law@redhat.com>
 
        * gcc.dg/Wbuiltin-declaration-mismatch-9.c: Improve pruning of
@@ -2489,20 +2461,6 @@
        * gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c: New test.
        * gcc.target/arm/multilib.exp: Add tests for -mcpu=cortex-m55.
 
-2020-10-05  Dennis Zhang  <dennis.zhang@arm.com>
-
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional
-       option -fno-ipa-icf and change the instruction count from 8 to 16.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise.
-       * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise.
-
 2020-10-05  Nathan Sidwell  <nathan@acm.org>
 
        * c-c++-common/spellcheck-reserved.c: Restore diagnostic.
Domain: System / Toolchain;