radv: store the DCC predicate for each mip

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e29ee70..a6b1f76 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1240,12 +1240,13 @@ static void
 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
                         int index,
                         struct radv_attachment_info *att,
-                        struct radv_image *image,
+                        struct radv_image_view *iview,
                         VkImageLayout layout)
 {
        bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
        struct radv_color_buffer_info *cb = &att->cb;
        uint32_t cb_color_info = cb->cb_color_info;
+       struct radv_image *image = iview->image;
 
        if (!radv_layout_dcc_compressed(image, layout,
                                        radv_image_queue_family_mask(image,
@@ -1295,7 +1296,15 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 
        if (radv_image_has_dcc(image)) {
                /* Drawing with DCC enabled also compresses colorbuffers. */
-               radv_update_dcc_metadata(cmd_buffer, image, true);
+               VkImageSubresourceRange range = {
+                       .aspectMask = iview->aspect_mask,
+                       .baseMipLevel = iview->base_mip,
+                       .levelCount = iview->level_count,
+                       .baseArrayLayer = iview->base_layer,
+                       .layerCount = iview->layer_count,
+               };
+
+               radv_update_dcc_metadata(cmd_buffer, image, &range, true);
        }
 }
 
@@ -1635,22 +1644,27 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
  */
 void
 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
-                        struct radv_image *image, bool value)
+                        struct radv_image *image,
+                        const VkImageSubresourceRange *range, bool value)
 {
        uint64_t pred_val = value;
-       uint64_t va = radv_buffer_get_va(image->bo);
-       va += image->offset + image->dcc_pred_offset;
+       uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
+       uint32_t level_count = radv_get_levelCount(image, range);
+       uint32_t count = 2 * level_count;
 
        assert(radv_image_has_dcc(image));
 
-       radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
+       radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
        radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
                                    S_370_WR_CONFIRM(1) |
                                    S_370_ENGINE_SEL(V_370_PFP));
        radeon_emit(cmd_buffer->cs, va);
        radeon_emit(cmd_buffer->cs, va >> 32);
-       radeon_emit(cmd_buffer->cs, pred_val);
-       radeon_emit(cmd_buffer->cs, pred_val >> 32);
+
+       for (uint32_t l = 0; l < level_count; l++) {
+               radeon_emit(cmd_buffer->cs, pred_val);
+               radeon_emit(cmd_buffer->cs, pred_val >> 32);
+       }
 }
 
 /**
@@ -1808,7 +1822,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 
                assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
                                                       VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
-               radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
+               radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
 
                radv_load_color_clear_metadata(cmd_buffer, image, i);
 
@@ -4891,14 +4905,15 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
 }
 
 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
-                        struct radv_image *image, uint32_t value)
+                        struct radv_image *image,
+                        const VkImageSubresourceRange *range, uint32_t value)
 {
        struct radv_cmd_state *state = &cmd_buffer->state;
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 
-       state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
+       state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
@@ -4940,7 +4955,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
                        need_decompress_pass = true;
                }
 
-               radv_initialize_dcc(cmd_buffer, image, value);
+               radv_initialize_dcc(cmd_buffer, image, range, value);
 
                radv_update_fce_metadata(cmd_buffer, image, range,
                                         need_decompress_pass);
@@ -4974,7 +4989,7 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe
 
        if (radv_image_has_dcc(image)) {
                if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
-                       radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
+                       radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
                } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
                           !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
                        radv_decompress_dcc(cmd_buffer, image, range);

diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 59b9121..d58b085 100644 (file)
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -216,7 +216,8 @@ uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
 uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
                          struct radv_image *image, uint32_t value);
 uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
-                       struct radv_image *image, uint32_t value);
+                       struct radv_image *image,
+                       const VkImageSubresourceRange *range, uint32_t value);
 uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
                          struct radv_image *image,
                          const VkImageSubresourceRange *range, uint32_t value);

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 269d047..8cacea0 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1335,10 +1335,11 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
 
 uint32_t
 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
-              struct radv_image *image, uint32_t value)
+              struct radv_image *image,
+              const VkImageSubresourceRange *range, uint32_t value)
 {
        /* Mark the image as being compressed. */
-       radv_update_dcc_metadata(cmd_buffer, image, true);
+       radv_update_dcc_metadata(cmd_buffer, image, range, true);
 
        return radv_fill_buffer(cmd_buffer, image->bo,
                                image->offset + image->dcc_offset,
@@ -1543,7 +1544,8 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
                if (!can_avoid_fast_clear_elim)
                        need_decompress_pass = true;
 
-               flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
+               flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, &range,
+                                            reset_value);
 
                radv_update_fce_metadata(cmd_buffer, iview->image, &range,
                                         need_decompress_pass);

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 46472ba..8fba2aa 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -716,7 +716,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 
                /* Mark the image as being decompressed. */
                if (decompress_dcc)
-                       radv_update_dcc_metadata(cmd_buffer, image, false);
+                       radv_update_dcc_metadata(cmd_buffer, image, subresourceRange, false);
        }
 
        radv_meta_restore(&saved_state, cmd_buffer);
@@ -822,7 +822,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
        radv_unaligned_dispatch(cmd_buffer, image->info.width, image->info.height, 1);
 
        /* Mark this image as actually being decompressed. */
-       radv_update_dcc_metadata(cmd_buffer, image, false);
+       radv_update_dcc_metadata(cmd_buffer, image, subresourceRange, false);
 
        /* The fill buffer below does its own saving */
        radv_meta_restore(&saved_state, cmd_buffer);
@@ -830,7 +830,8 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
        state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
                             RADV_CMD_FLAG_INV_VMEM_L1;
 
-       state->flush_bits |= radv_clear_dcc(cmd_buffer, image, 0xffffffff);
+       state->flush_bits |= radv_clear_dcc(cmd_buffer, image, subresourceRange,
+                                           0xffffffff);
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;

diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index 8c4bfa6..73a4bbe 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -463,9 +463,6 @@ void radv_CmdResolveImage(
        if (src_image->info.array_size > 1)
                radv_finishme("vkCmdResolveImage: multisample array images");
 
-       if (radv_image_has_dcc(dest_image)) {
-               radv_initialize_dcc(cmd_buffer, dest_image, 0xffffffff);
-       }
        unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
        for (uint32_t r = 0; r < region_count; ++r) {
                const VkImageResolve *region = &regions[r];
@@ -509,6 +506,17 @@ void radv_CmdResolveImage(
                const struct VkOffset3D dstOffset =
                        radv_sanitize_image_offset(dest_image->type, region->dstOffset);
 
+               if (radv_image_has_dcc(dest_image)) {
+                       VkImageSubresourceRange range = {
+                               .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
+                               .baseMipLevel = region->dstSubresource.mipLevel,
+                               .levelCount = 1,
+                               .baseArrayLayer = dest_base_layer,
+                               .layerCount = region->dstSubresource.layerCount,
+                       };
+
+                       radv_initialize_dcc(cmd_buffer, dest_image, &range, 0xffffffff);
+               }
 
                for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
                     ++layer) {
@@ -669,7 +677,15 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
                struct radv_image *dst_img = dest_iview->image;
 
                if (radv_image_has_dcc(dst_img)) {
-                       radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
+                       VkImageSubresourceRange range = {
+                               .aspectMask = dest_iview->aspect_mask,
+                               .baseMipLevel = dest_iview->base_mip,
+                               .levelCount = dest_iview->level_count,
+                               .baseArrayLayer = dest_iview->base_layer,
+                               .layerCount = dest_iview->layer_count,
+                       };
+
+                       radv_initialize_dcc(cmd_buffer, dst_img, &range, 0xffffffff);
                        cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
                }
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e9ad3d2..0f20cbe 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1261,7 +1261,8 @@ void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
                              const VkImageSubresourceRange *range, bool value);
 
 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
-                             struct radv_image *image, bool value);
+                             struct radv_image *image,
+                             const VkImageSubresourceRange *range, bool value);
 
 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
                          struct radeon_winsys_bo *bo,
@@ -1700,6 +1701,15 @@ radv_image_get_fce_pred_va(const struct radv_image *image,
        return va;
 }
 
+static inline uint64_t
+radv_image_get_dcc_pred_va(const struct radv_image *image,
+                          uint32_t base_level)
+{
+       uint64_t va = radv_buffer_get_va(image->bo);
+       va += image->offset + image->dcc_pred_offset + base_level * 8;
+       return va;
+}
+
 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
 
 static inline uint32_t
@@ -2017,7 +2027,8 @@ void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
                                    const VkWriteDescriptorSet *pDescriptorWrites);
 
 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
-                        struct radv_image *image, uint32_t value);
+                        struct radv_image *image,
+                        const VkImageSubresourceRange *range, uint32_t value);
 
 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
                           struct radv_image *image);