nir/lower_tex: ignore width of cube textures

On AMD hardware, height is faster to access and we're already doing so.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17991>

diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
index 9add854..634384f 100644 (file)
--- a/src/compiler/nir/nir_lower_tex.c
+++ b/src/compiler/nir/nir_lower_tex.c
@@ -1254,7 +1254,7 @@ nir_lower_txs_cube_array(nir_builder *b, nir_tex_instr *tex)
    assert(tex->dest.is_ssa);
    assert(tex->dest.ssa.num_components == 3);
    nir_ssa_def *size = &tex->dest.ssa;
-   size = nir_vec3(b, nir_channel(b, size, 0),
+   size = nir_vec3(b, nir_channel(b, size, 1),
                       nir_channel(b, size, 1),
                       nir_idiv(b, nir_channel(b, size, 2),
                                   nir_imm_int(b, 6)));