PM / sprd: Remove build warnings

This patch removes build warnings caused by making pointers from integer
without casts, unexpected types of function arguments, unused
variables/functions, using variables without initialization, using wrong
printk format strings, and -Wreturn-type.

Change-Id: Ic08fc5384235643ebeae2bf13c9609013c781563
Signed-off-by: Wook Song <wook16.song@samsung.com>

diff --git a/drivers/platform/sprd/pm-scx35.c b/drivers/platform/sprd/pm-scx35.c
index 726127c..502cc03 100644 (file)
--- a/drivers/platform/sprd/pm-scx35.c
+++ b/drivers/platform/sprd/pm-scx35.c
@@ -148,7 +148,7 @@ static unsigned long ana_chip_id;
  * bit_4 : ap sys
  * bit_5 : dcdc arm
 */
-static  struct auto_pd_en pd_config = {
+static __maybe_unused struct auto_pd_en pd_config = {
        0x6a6aa6a6, 0x3f,0xa6a66a6a,
        .pd_config_menu = {
        "ca7_top",
@@ -860,20 +860,30 @@ void bak_last_reg(void)
        cp0_power_domain_debug();
        cp1_power_domain_debug();
 #endif
-       pd_pub_sys = __raw_readl(REG_PMU_APB_PD_PUB_SYS_CFG);
-       cp_slp_status_dbg0 = __raw_readl(REG_PMU_APB_CP_SLP_STATUS_DBG0);
+       pd_pub_sys = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_PD_PUB_SYS_CFG);
+       cp_slp_status_dbg0 = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_CP_SLP_STATUS_DBG0);
 #if !defined(CONFIG_ARCH_SCX35L)
-       cp_slp_status_dbg1 = __raw_readl(REG_PMU_APB_CP_SLP_STATUS_DBG1);
-#endif
-       pwr_stat0 = __raw_readl(REG_PMU_APB_PWR_STATUS0_DBG);
-       pwr_stat1 = __raw_readl(REG_PMU_APB_PWR_STATUS1_DBG);
-       pwr_stat2 = __raw_readl(REG_PMU_APB_PWR_STATUS2_DBG);
+       cp_slp_status_dbg1 = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_CP_SLP_STATUS_DBG1);
+#endif
+       pwr_stat0 = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_PWR_STATUS0_DBG);
+       pwr_stat1 = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_PWR_STATUS1_DBG);
+       pwr_stat2 = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_PWR_STATUS2_DBG);
 #if !defined(CONFIG_ARCH_SCX35L)
-       pwr_stat3 = __raw_readl(REG_PMU_APB_PWR_STATUS3_DBG);
+       pwr_stat3 = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_PWR_STATUS3_DBG);
 #endif
-       sleep_ctrl = __raw_readl(REG_PMU_APB_SLEEP_CTRL);
-       ddr_sleep_ctrl = __raw_readl(REG_PMU_APB_DDR_SLEEP_CTRL);
-       sleep_status = __raw_readl(REG_PMU_APB_SLEEP_STATUS);
+       sleep_ctrl = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_SLEEP_CTRL);
+       ddr_sleep_ctrl = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_DDR_SLEEP_CTRL);
+       sleep_status = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_SLEEP_STATUS);
 
 #if defined(CONFIG_ARCH_SCX15)
        xtl0_rel_cfg = __raw_readl(REG_PMU_APB_XTL0_REL_CFG);
@@ -892,21 +902,25 @@ void bak_last_reg(void)
        ddr_chn_sleep_ctrl1 = __raw_readl(REG_PMU_APB_DDR_CHN_SLEEP_CTRL1);
 #endif
 
-       apb_eb0 = __raw_readl(REG_AON_APB_APB_EB0);
-       apb_eb1 = __raw_readl(REG_AON_APB_APB_EB1);
-       pwr_ctrl = __raw_readl(REG_AON_APB_PWR_CTRL);
+       apb_eb0 = __raw_readl((void __iomem __force *)REG_AON_APB_APB_EB0);
+       apb_eb1 = __raw_readl((void __iomem __force *)REG_AON_APB_APB_EB1);
+       pwr_ctrl = __raw_readl((void __iomem __force *)REG_AON_APB_PWR_CTRL);
 
-       ahb_eb = __raw_readl(REG_AP_AHB_AHB_EB);
+       ahb_eb = __raw_readl((void __iomem __force *)REG_AP_AHB_AHB_EB);
 
-       apb_eb = __raw_readl(REG_AP_APB_APB_EB);
-       mcu_pause = __raw_readl(REG_AP_AHB_MCU_PAUSE);
-       sys_force_sleep = __raw_readl(REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG);
-       sys_auto_sleep_cfg = __raw_readl(REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG);
+       apb_eb = __raw_readl((void __iomem __force *)REG_AP_APB_APB_EB);
+       mcu_pause = __raw_readl((void __iomem __force *)
+                       REG_AP_AHB_MCU_PAUSE);
+       sys_force_sleep = __raw_readl((void __iomem __force *)
+                       REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG);
+       sys_auto_sleep_cfg = __raw_readl((void __iomem __force *)
+                       REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG);
        //ca7_standby_status = __raw_readl(REG_AP_AHB_CA7_STANDBY_STATUS);
 #if defined(CONFIG_ARCH_SCX35LT8)
        ca7_standby_status = __raw_readl(REG_AP_AHB_APCPU_STANDBY_STATUS);
 #else
-       ca7_standby_status = __raw_readl(REG_AP_AHB_CA7_STANDBY_STATUS);
+       ca7_standby_status = __raw_readl((void __iomem __force *)
+                       REG_AP_AHB_CA7_STANDBY_STATUS);
 #endif
 
 #if defined(CONFIG_ADIE_SC2713S) || defined(CONFIG_ADIE_SC2713)
@@ -1154,10 +1168,11 @@ static unsigned long *vtest = NULL;
 static unsigned long *ptest = NULL;
 static void test_memory(void)
 {
-       int i;
 #ifndef CONFIG_ARCH_SCX30G
        vtest = kmalloc(64*1024, GFP_KERNEL);
        if (vtest) {
+               int i;
+
                for (i = 0; i < (64*1024/4); i++) {
                        vtest[i] = 0x12345678;
                }
@@ -1166,12 +1181,13 @@ static void test_memory(void)
        if (vtest) {
                vtest[0] = 0x12345678;
 #endif
-               printk("%s %p %p\n", __func__, vtest, virt_to_phys(vtest));
-               ptest = virt_to_phys(vtest);
+               printk("%s %p %p\n",
+                               __func__, vtest, (void *)virt_to_phys(vtest));
+               ptest = (unsigned long *)virt_to_phys(vtest);
        } else {
                printk("error kmalloc\n");
        }
-       sp_pm_reset_vector[64] = ptest;
+       sp_pm_reset_vector[64] = (unsigned int )ptest;
 }
 #endif
 
@@ -1195,9 +1211,13 @@ void restore_reset_vector(void)
 })
 
 #if !(defined(CONFIG_ARCH_SCX35L64)||defined(CONFIG_ARCH_SCX35LT8))
-u32 __attribute__ ((naked)) read_cpsr(void)
+u32 read_cpsr(void)
 {
-       __asm__ __volatile__("mrs r0, cpsr\nbx lr");
+       u32 ret;
+
+       __asm__ __volatile__("mrs %0, cpsr" : "=r" (ret));
+
+       return ret;
 }
 #endif
 /* make sure printk is end, if not maybe some messy code  in SERIAL1 output */
@@ -1211,24 +1231,24 @@ static __used void wait_until_uart1_tx_done(void)
        u32 really_done = 0;
        u32 timeout = 2000;
 
-       tx_fifo_val = __raw_readl(UART_STS1);
+       tx_fifo_val = __raw_readl((void __iomem __force *)UART_STS1);
        tx_fifo_val >>= 8;
        tx_fifo_val &= 0xff;
        while(tx_fifo_val != 0) {
                if (timeout <= 0) break;
                udelay(100);
-               tx_fifo_val = __raw_readl(UART_STS1);
+               tx_fifo_val = __raw_readl((void __iomem __force *)UART_STS1);
                tx_fifo_val >>= 8;
                tx_fifo_val &= 0xff;
                timeout--;
        }
 
        timeout = 30;
-       really_done = __raw_readl(UART_STS0);
+       really_done = __raw_readl((void __iomem __force *)UART_STS0);
        while(!(really_done & UART_TRANSFER_REALLY_OVER)) {
                if (timeout <= 0) break;
                udelay(100);
-               really_done = __raw_readl(UART_STS0);
+               really_done = __raw_readl((void __iomem __force *)UART_STS0);
                timeout--;
        }
 }
@@ -1371,7 +1391,8 @@ int deep_sleep(int from_idle)
                sci_glb_set(REG_AON_APB_ARM7_CFG_BUS, BIT_ARM7_CFG_BUS_SLEEP);
 #else
 #if !(defined(CONFIG_ARCH_SCX35L64)||defined(CONFIG_ARCH_SCX35LT8))
-               __raw_writel(0x0, REG_PMU_APB_CA7_C0_CFG);
+               __raw_writel(0x0,
+                       (void __iomem __force *) REG_PMU_APB_CA7_C0_CFG);
 #endif
 #endif
                show_deep_reg_status();
@@ -1440,7 +1461,8 @@ int deep_sleep(int from_idle)
                __raw_writel(0x30, REG_ARM7_AHB_RF_AP_COMM_CTL);
 #else
 #if !(defined(CONFIG_ARCH_SCX35L64)||defined(CONFIG_ARCH_SCX35LT8))
-               __raw_writel(0x1, REG_PMU_APB_CA7_C0_CFG);
+               __raw_writel(0x1,
+                       (void __iomem __force *)REG_PMU_APB_CA7_C0_CFG);
 #endif
 #endif
                pr_debug("ret %d not from idle\n", ret);
@@ -1561,10 +1583,10 @@ void sc_default_idle(void)
 /*config dcdc core deep sleep voltage*/
 static void dcdc_core_ds_config(void)
 {
+#if defined(CONFIG_ADIE_SC2713S) || defined(CONFIG_ADIE_SC2713)
        u32 dcdc_core_ctl_adi = 0;
        u32 val = 0;
        u32 dcdc_core_ctl_ds = -1;
-#if defined(CONFIG_ADIE_SC2713S) || defined(CONFIG_ADIE_SC2713)
 #ifdef CONFIG_ARCH_SCX30G
        static struct dcdc_core_ds_step_info step_info[5]={
                {0, 0,0, 0},

diff --git a/drivers/platform/sprd/pm_debug_scx35.c b/drivers/platform/sprd/pm_debug_scx35.c
index 38f6b13..42aac37 100644 (file)
--- a/drivers/platform/sprd/pm_debug_scx35.c
+++ b/drivers/platform/sprd/pm_debug_scx35.c
@@ -144,25 +144,41 @@ static void parse_hard_irq(unsigned long val, unsigned long intc)
 
 void hard_irq_set(void)
 {
-       sprd_irqs_sts[0] = __raw_readl(INT_IRQ_STS);
-       sprd_irqs_sts[1] = __raw_readl(INT_FIQ_STS);
-       irq_status = __raw_readl(INTCV0_IRQ_RAW);
+       sprd_irqs_sts[0] = __raw_readl((void __iomem __force *)INT_IRQ_STS);
+       sprd_irqs_sts[1] = __raw_readl((void __iomem __force *)INT_FIQ_STS);
+       irq_status = __raw_readl((void __iomem __force *)INTCV0_IRQ_RAW);
        parse_hard_irq(irq_status, 0);
-       irq_status = __raw_readl(INTCV1_IRQ_RAW);
+       irq_status = __raw_readl((void __iomem __force *)INTCV1_IRQ_RAW);
        parse_hard_irq(irq_status, 1);
-       irq_status = __raw_readl(INTCV2_IRQ_RAW);
+       irq_status = __raw_readl((void __iomem __force *)INTCV2_IRQ_RAW);
        parse_hard_irq(irq_status, 2);
-       irq_status = __raw_readl(INTCV3_IRQ_RAW);
+       irq_status = __raw_readl((void __iomem __force *)INTCV3_IRQ_RAW);
        parse_hard_irq(irq_status, 3);
 }
 void print_int_status(void)
 {
-       pr_debug("APB_EB 0x%08x\n", __raw_readl(REG_AP_APB_APB_EB));
-       pr_debug("INTC0 mask:0x%08x raw:0x%08x en:0x%08x\n", __raw_readl(INTCV0_IRQ_MSKSTS),__raw_readl(INTCV0_IRQ_RAW), __raw_readl(INTCV0_IRQ_EN));
-       pr_debug("INTC1 mask:0x%08x raw:0x%08x en:0x%08x\n", __raw_readl(INTCV1_IRQ_MSKSTS),__raw_readl(INTCV1_IRQ_RAW), __raw_readl(INTCV1_IRQ_EN));
-       pr_debug("INTC2 mask:0x%08x raw:0x%08x en:0x%08x\n", __raw_readl(INTCV2_IRQ_MSKSTS),__raw_readl(INTCV2_IRQ_RAW), __raw_readl(INTCV2_IRQ_EN));
-       pr_debug("INTC3 mask:0x%08x raw:0x%08x en:0x%08x\n", __raw_readl(INTCV3_IRQ_MSKSTS),__raw_readl(INTCV3_IRQ_RAW), __raw_readl(INTCV3_IRQ_EN));
-       pr_debug("INT mask:0x%08x raw:0x%08x en:0x%08x\n", __raw_readl(INT_IRQ_STS),__raw_readl(INT_IRQ_RAW), __raw_readl(INT_IRQ_ENB));
+       pr_debug("APB_EB 0x%08x\n",
+                       __raw_readl((void __iomem __force *)REG_AP_APB_APB_EB));
+       pr_debug("INTC0 mask:0x%08x raw:0x%08x en:0x%08x\n",
+                       __raw_readl((void __iomem __force *)INTCV0_IRQ_MSKSTS),
+                       __raw_readl((void __iomem __force *)INTCV0_IRQ_RAW),
+                       __raw_readl((void __iomem __force *)INTCV0_IRQ_EN));
+       pr_debug("INTC1 mask:0x%08x raw:0x%08x en:0x%08x\n",
+                       __raw_readl((void __iomem __force *)INTCV1_IRQ_MSKSTS),
+                       __raw_readl((void __iomem __force *)INTCV1_IRQ_RAW),
+                       __raw_readl((void __iomem __force *)INTCV1_IRQ_EN));
+       pr_debug("INTC2 mask:0x%08x raw:0x%08x en:0x%08x\n",
+                       __raw_readl((void __iomem __force *)INTCV2_IRQ_MSKSTS),
+                       __raw_readl((void __iomem __force *)INTCV2_IRQ_RAW),
+                       __raw_readl((void __iomem __force *)INTCV2_IRQ_EN));
+       pr_debug("INTC3 mask:0x%08x raw:0x%08x en:0x%08x\n",
+                       __raw_readl((void __iomem __force *)INTCV3_IRQ_MSKSTS),
+                       __raw_readl((void __iomem __force *)INTCV3_IRQ_RAW),
+                       __raw_readl((void __iomem __force *)INTCV3_IRQ_EN));
+       pr_debug("INT mask:0x%08x raw:0x%08x en:0x%08x\n",
+                       __raw_readl((void __iomem __force *)INT_IRQ_STS),
+                       __raw_readl((void __iomem __force *)INT_IRQ_RAW),
+                       __raw_readl((void __iomem __force *)INT_IRQ_ENB));
        pr_debug("ANA INT mask:0x%08x raw:0x%08x en:0x%08x\n", sci_adi_read(ANA_REG_INT_MASK_STATUS), sci_adi_read(ANA_REG_INT_RAW_STATUS), sci_adi_read(ANA_REG_INT_EN));
        pr_debug("ANA EIC MODULE_EN 0x%08x eic bit(3)\n", sci_adi_read(ANA_REG_GLB_ARM_MODULE_EN));
        pr_debug("ANA EIC int en 0x%08x\n", sci_adi_read(ANA_CTL_EIC_BASE + 0x18));
@@ -362,8 +378,12 @@ void print_hard_irq_inloop(int ret)
        if (sprd_hard_irq[35]) {
                for(i=0; i<(GPIO_GROUP_NUM/2); i++){
                        j = 2*i;
-                       gpio_irq[j]= __raw_readl(SPRD_GPIO_BASE + 0x100*i + REG_GPIO_MIS);
-                       gpio_irq[j+1]= __raw_readl(SPRD_GPIO_BASE + 0x100*i + 0x80 + REG_GPIO_MIS);
+                       gpio_irq[j]= __raw_readl((void __iomem __force *)
+                                       (SPRD_GPIO_BASE + 0x100 * i
+                                        + REG_GPIO_MIS));
+                       gpio_irq[j+1]= __raw_readl((void __iomem __force *)
+                                       (SPRD_GPIO_BASE + 0x100 * i
+                                        + 0x80 + REG_GPIO_MIS));
        //              printk("gpio_irq[%d]:0x%x, gpio_irq[%d]:0x%x \n", j, gpio_irq[j], j+1, gpio_irq[j+1]);
                }
                for(i=0; i<GPIO_GROUP_NUM; i++){
@@ -381,10 +401,8 @@ void print_hard_irq_inloop(int ret)
                }
        }
 
-       if (interrupt_strings) {
-               interrupt_strings[WAKEUP_BY_STRING -1] = '\0';
-               sleep_history_marker(SLEEP_HISTORY_WAKEUP_IRQ, NULL, interrupt_strings);
-       }
+       interrupt_strings[WAKEUP_BY_STRING -1] = '\0';
+       sleep_history_marker(SLEEP_HISTORY_WAKEUP_IRQ, NULL, interrupt_strings);
 #endif
 }
 
@@ -576,10 +594,10 @@ static void print_debug_info(void)
 {
        unsigned int ahb_eb, apb_eb0, cp_slp_status0, cp_slp_status1, ldo_pd_ctrl,
                        ap_apb_eb, apb_pwrstatus0, apb_pwrstatus1, apb_pwrstatus2,
-                       apb_pwrstatus3, mpll_cfg, dpll_cfg, emc_clk_cfg,
+                       apb_pwrstatus3, emc_clk_cfg,
                        apb_slp_status, ap_sys_auto_sleep_cfg, ca5_lte_status;
 #if defined(CONFIG_ARCH_SCX15)
-       unsigned int ldo_dcdc_pd_ctrl;
+       unsigned int ldo_dcdc_pd_ctrl, mpll_cfg, dpll_cfg;
 #endif
 #if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L)
        unsigned int mpll_cfg1, dpll_cfg1, aon_apb_eb1;
@@ -587,6 +605,8 @@ static void print_debug_info(void)
 #if defined(CONFIG_ARCH_SCX35L)
        unsigned int mpll_cfg2, dpll_cfg2;
 #endif
+       u32 sleep_ctrl;
+
        ahb_eb = sci_glb_read(REG_AP_AHB_AHB_EB, -1UL);
        ap_sys_auto_sleep_cfg = sci_glb_read(REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG, -1UL);
        ap_apb_eb = sci_glb_read(REG_AP_APB_APB_EB, -1UL);
@@ -605,7 +625,8 @@ static void print_debug_info(void)
 #if defined(CONFIG_ARCH_SCX35LT8)
        apb_pwrstatus3 = sci_glb_read(REG_PMU_APB_PWR_STATUS3_DBG, -1UL);
 #endif
-       apb_slp_status = __raw_readl(REG_PMU_APB_SLEEP_STATUS);
+       apb_slp_status = __raw_readl((void __iomem __force *)
+                       REG_PMU_APB_SLEEP_STATUS);
 #if defined(CONFIG_ARCH_SCX15)
        mpll_cfg = sci_glb_read(REG_AON_APB_MPLL_CFG, -1UL);
        dpll_cfg = sci_glb_read(REG_AON_APB_DPLL_CFG, -1UL);
@@ -624,7 +645,8 @@ static void print_debug_info(void)
 #if defined(CONFIG_ARCH_SCX15)
        ldo_dcdc_pd_ctrl = sci_adi_read(ANA_REG_GLB_LDO_DCDC_PD);
 #endif
-       unsigned long sleep_ctrl = __raw_readl(REG_PMU_APB_SLEEP_CTRL);
+       sleep_ctrl = __raw_readl((void __iomem __force *)
+                                       REG_PMU_APB_SLEEP_CTRL);
        printk("###---- REG_PMU_APB_SLEEP_CTRL : 0x%08x\n", sleep_ctrl);
        printk("###---- REG_AP_AHB_AHB_EB : 0x%08x\n", ahb_eb);
        printk("###---- REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG : 0x%08x\n", ap_sys_auto_sleep_cfg);
@@ -643,7 +665,7 @@ static void print_debug_info(void)
        printk("###---- REG_PMU_APB_PWR_STATUS3_DBG : 0x%08x\n", apb_pwrstatus3);
        printk("###---- REG_PMU_APB_SLEEP_STATUS : 0x%08x\n", apb_slp_status);
        printk("###---- REG_PUB_APB_DDR_ID2QOS_RCFG9 : 0x%08x\n", ca5_lte_status);
-#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ARCH_SCX35) || defined(CONFIG_ARCH_SCX30G)
+#if defined(CONFIG_ARCH_SCX15)
        printk("###---- REG_AON_APB_MPLL_CFG : 0x%08x\n", mpll_cfg);
        printk("###---- REG_AON_APB_DPLL_CFG : 0x%08x\n", dpll_cfg);
 #endif

diff --git a/include/soc/sprd/pm_debug.h b/include/soc/sprd/pm_debug.h
index c91bb33..1ae61ea 100644 (file)
--- a/include/soc/sprd/pm_debug.h
+++ b/include/soc/sprd/pm_debug.h
@@ -15,11 +15,11 @@
 static u32 inline get_sys_cnt(void)
 {
        u32 val1, val2;
-        val1 = __raw_readl(SYSCNT_COUNT);
-        val2 = __raw_readl(SYSCNT_COUNT);
+        val1 = __raw_readl((void __iomem __force *)SYSCNT_COUNT);
+        val2 = __raw_readl((void __iomem __force *)SYSCNT_COUNT);
         while(val2 != val1) {
              val1 = val2;
-             val2 = __raw_readl(SYSCNT_COUNT);
+             val2 = __raw_readl((void __iomem __force *)SYSCNT_COUNT);
         }
         return val2;
 }