drm/i915/gt: Avoid multi-LRI on Sandybridge

Sandybridge is the gen that didn't handle multiple registers in a single
LRI packet. Don't forget it!

Fixes: 902eb748e5c3 ("drm/i915/gt: Tidy up full-ppgtt on Ivybridge")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Tested-by: Tomi Sarvela <tomi.p.sarvela@intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191217091328.3093551-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 00d1fb582e95cd8fa80a52dd9395c0a20ccdebf1..b14d69d60e008f8b2da337cd05d05b7f2a2a25f9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1370,17 +1370,17 @@ static int load_pd_dir(struct i915_request *rq,
        const struct intel_engine_cs * const engine = rq->engine;
        u32 *cs;
 
-       cs = intel_ring_begin(rq, 10);
+       cs = intel_ring_begin(rq, 12);
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
-       *cs++ = MI_LOAD_REGISTER_IMM(3);
+       *cs++ = MI_LOAD_REGISTER_IMM(1);
        *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
        *cs++ = valid;
+
+       *cs++ = MI_LOAD_REGISTER_IMM(1);
        *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
        *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
-       *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
-       *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
 
        /* Stall until the page table load is complete? */
        *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
@@ -1388,6 +1388,10 @@ static int load_pd_dir(struct i915_request *rq,
        *cs++ = intel_gt_scratch_offset(engine->gt,
                                        INTEL_GT_SCRATCH_FIELD_DEFAULT);
 
+       *cs++ = MI_LOAD_REGISTER_IMM(1);
+       *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
+       *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
+
        intel_ring_advance(rq, cs);
 
        return 0;