Prepare GCC for a future architecture extension.
gcc/ChangeLog:
* common/config/s390/s390-common.c (processor_flags_table): New entry.
* config.gcc: Enable arch14 for --with-arch and --with-tune.
* config/s390/driver-native.c (s390_host_detect_local_cpu): Pick
arch14 for unknown CPU models.
* config/s390/s390-opts.h (enum processor_type): Add PROCESSOR_ARCH14.
* config/s390/s390.c (s390_issue_rate): Add case for PROCESSOR_ARCH14.
(s390_get_sched_attrmask): Likewise.
(s390_get_unit_mask): Likewise.
* config/s390/s390.h (enum processor_flags): Add PF_NNPA and PF_ARCH14.
(TARGET_CPU_ARCH14, TARGET_CPU_ARCH14_P, TARGET_CPU_NNPA)
(TARGET_CPU_NNPA_P, TARGET_ARCH14, TARGET_ARCH14_P, TARGET_NNPA)
(TARGET_NNPA_P): New macro definitions.
* config/s390/s390.md ("cpu_facility", "enabled"): Add arch14 and nnpa.
* config/s390/s390.opt: Add PROCESSOR_ARCH14.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add check for nnpa facility.
| PF_Z13 | PF_VX | PF_VXE | PF_Z14,
/* z15 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
| PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
+ | PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15,
+ /* arch14 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
+ | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
| PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15
+ | PF_NNPA | PF_ARCH14
};
/* Change optimizations to be performed, depending on the
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
- "" | native | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12 | z13 | z14 | z15 | arch5 | arch6 | arch7 | arch8 | arch9 | arch10 | arch11 | arch12 | arch13 )
+ "" | native | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12 | z13 | z14 | z15 | arch5 | arch6 | arch7 | arch8 | arch9 | arch10 | arch11 | arch12 | arch13 | arch14 )
# OK
;;
*)
cpu = "z15";
break;
default:
- cpu = "z15";
+ cpu = "arch14";
break;
}
}
PROCESSOR_2964_Z13,
PROCESSOR_3906_Z14,
PROCESSOR_8561_Z15,
+ PROCESSOR_ARCH14,
PROCESSOR_NATIVE,
PROCESSOR_max
};
{ "z13", "z13", PROCESSOR_2964_Z13, &zEC12_cost, 11 },
{ "z14", "arch12", PROCESSOR_3906_Z14, &zEC12_cost, 12 },
{ "z15", "arch13", PROCESSOR_8561_Z15, &zEC12_cost, 13 },
+ { "arch14", "", PROCESSOR_ARCH14, &zEC12_cost, 14 },
{ "native", "", PROCESSOR_NATIVE, NULL, 0 }
};
case PROCESSOR_2827_ZEC12:
case PROCESSOR_2964_Z13:
case PROCESSOR_3906_Z14:
+ case PROCESSOR_ARCH14:
default:
return 1;
}
mask |= S390_SCHED_ATTR_MASK_GROUPOFTWO;
break;
case PROCESSOR_8561_Z15:
+ case PROCESSOR_ARCH14:
if (get_attr_z15_cracked (insn))
mask |= S390_SCHED_ATTR_MASK_CRACKED;
if (get_attr_z15_expanded (insn))
mask |= 1 << 3;
break;
case PROCESSOR_8561_Z15:
+ case PROCESSOR_ARCH14:
*units = 4;
if (get_attr_z15_unit_lsu (insn))
mask |= 1 << 0;
PF_Z14 = 2048,
PF_VXE = 4096,
PF_VXE2 = 8192,
- PF_Z15 = 16384
+ PF_Z15 = 16384,
+ PF_NNPA = 32768,
+ PF_ARCH14 = 65536
};
/* This is necessary to avoid a warning about comparing different enum
(s390_arch_flags & PF_VXE2)
#define TARGET_CPU_VXE2_P(opts) \
(opts->x_s390_arch_flags & PF_VXE2)
+#define TARGET_CPU_ARCH14 \
+ (s390_arch_flags & PF_ARCH14)
+#define TARGET_CPU_ARCH14_P(opts) \
+ (opts->x_s390_arch_flags & PF_ARCH14)
+#define TARGET_CPU_NNPA \
+ (s390_arch_flags & PF_NNPA)
+#define TARGET_CPU_NNPA_P(opts) \
+ (opts->x_s390_arch_flags & PF_NNPA)
#define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts))
(TARGET_VX && TARGET_CPU_VXE2)
#define TARGET_VXE2_P(opts) \
(TARGET_VX_P (opts) && TARGET_CPU_VXE2_P (opts))
+#define TARGET_ARCH14 (TARGET_ZARCH && TARGET_CPU_ARCH14)
+#define TARGET_ARCH14_P(opts) \
+ (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ARCH14_P (opts))
+#define TARGET_NNPA \
+ (TARGET_ZARCH && TARGET_CPU_NNPA)
+#define TARGET_NNPA_P(opts) \
+ (TARGET_ZARCH_P (opts) && TARGET_CPU_NNPA_P (opts))
+
#if defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13)
#define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z13
#elif defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS)
(const (symbol_ref "s390_tune_attr")))
(define_attr "cpu_facility"
- "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2"
+ "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2,arch14,nnpa"
(const_string "standard"))
(define_attr "enabled" ""
(and (eq_attr "cpu_facility" "vxe2")
(match_test "TARGET_VXE2"))
(const_int 1)
- ]
+
+ (and (eq_attr "cpu_facility" "arch14")
+ (match_test "TARGET_ARCH14"))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "nnpa")
+ (match_test "TARGET_NNPA"))
+ (const_int 1)
+]
(const_int 0)))
;; Whether an instruction supports relative long addressing.
Enum(processor_type) String(arch13) Value(PROCESSOR_8561_Z15)
EnumValue
+Enum(processor_type) String(arch14) Value(PROCESSOR_ARCH14)
+
+EnumValue
Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
mbackchain
} "-march=arch13 -mzarch" ]
}
+# Same as above but for the arch14 NNPA facility.
+proc check_effective_target_s390_nnpa { } {
+ if ![istarget s390*-*-*] then {
+ return 0;
+ }
+
+ return [check_runtime s390_check_nnpa {
+ int main (void)
+ {
+ asm ("vzero %%v24\n\t"
+ "vcrnf %%v24,%%v24,%%v24,0,2" : : : "v24");
+ return 0;
+ }
+ } "-march=arch14 -mzarch" ]
+}
+
#For versions of ARM architectures that have hardware div insn,
#disable the divmod transform