drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c (v2)

[ Upstream commit c37243579d6c881c575dcfb54cf31c9ded88f946 ]

We might get different numbers of clocks from powerplay depending
on what the OEM has populated.

v2: add assert for at least one level

Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57..c9a241f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1438,6 +1438,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
        struct dc_context *ctx = dc->ctx;
        struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
        bool res;
+       unsigned vmin0p65_idx, vmid0p72_idx, vnom0p8_idx, vmax0p9_idx;
 
        /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
        res = dm_pp_get_clock_levels_by_type_with_voltage(
@@ -1449,17 +1450,28 @@ void dcn_bw_update_from_pplib(struct dc *dc)
                res = verify_clock_values(&fclks);
 
        if (res) {
-               ASSERT(fclks.num_levels >= 3);
-               dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
-               dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
-                               (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
-                               * ddr4_dram_factor_single_Channel / 1000.0;
-               dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
-                               (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
-                               * ddr4_dram_factor_single_Channel / 1000.0;
-               dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
-                               (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
-                               * ddr4_dram_factor_single_Channel / 1000.0;
+               ASSERT(fclks.num_levels);
+
+               vmin0p65_idx = 0;
+               vmid0p72_idx = fclks.num_levels -
+                       (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
+               vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
+               vmax0p9_idx = fclks.num_levels - 1;
+
+               dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
+                       32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
+               dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
+                       dc->dcn_soc->number_of_channels *
+                       (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
+                       * ddr4_dram_factor_single_Channel / 1000.0;
+               dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
+                       dc->dcn_soc->number_of_channels *
+                       (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
+                       * ddr4_dram_factor_single_Channel / 1000.0;
+               dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
+                       dc->dcn_soc->number_of_channels *
+                       (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
+                       * ddr4_dram_factor_single_Channel / 1000.0;
        } else
                BREAK_TO_DEBUGGER();