gfx: set power state

The PVR PCI PMCSR returns 0 (D0), even when the
device is actually in D3.  The PCI sub-system will
not D0 a device it thinks is already in D0; and
so the driver needs to make the calls to set the
power state directly to work around this failure
of PVR to be PCI compliant.

This change allows enabling the s0i1-idle state.

echo 5 > /sys/module/intel_idle/parameters/max_cstate
(currently the default is limited to 4, which is C6)

Issue: GRA-27
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c
index 3cc10c1..2f8c850 100644 (file)
--- a/drivers/staging/mrst/drv/psb_powermgmt.c
+++ b/drivers/staging/mrst/drv/psb_powermgmt.c
@@ -933,6 +933,8 @@ int ospm_power_suspend(struct device *dev)
         * status?!
         */
 
+       pci_save_state(pdev);
+       pci_set_power_state(pdev, PCI_D3hot);
 out:
        mutex_unlock(&g_ospm_mutex);
        return ret;
@@ -1032,6 +1034,8 @@ int ospm_power_resume(struct device *dev)
 
        ospm_resume_pci(pdev);
 
+       pci_set_power_state(pdev, PCI_D0);
+       pci_restore_state(pdev);
        ospm_resume_display(drm_dev);
        psb_irq_preinstall_islands(drm_dev, OSPM_DISPLAY_ISLAND);
        psb_irq_postinstall_islands(drm_dev, OSPM_DISPLAY_ISLAND);