* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in

order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.

* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb)  field coding types
and use it to encode register pair numbers when required.

* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.

* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.

* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index cc6d283..bbc5774 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+       PR gas/15095
+       * config/tc-tic6x.c (tic6x_try_encode): Handle
+       tic6x_coding_dreg_(msb|lsb) field coding types and use it to
+       encode register pair numbers when required.
+
 2013-03-15  Will Newton  <will.newton@linaro.org>
 
        * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register

diff --git a/gas/config/tc-tic6x.c b/gas/config/tc-tic6x.c
index 65517a6..7e11d0b 100644 (file)
--- a/gas/config/tc-tic6x.c
+++ b/gas/config/tc-tic6x.c
@@ -1,6 +1,5 @@
 /* TI C6X assembler.
-   Copyright 2010, 2011, 2012
-   Free Software Foundation, Inc.
+   Copyright 2010-2013 Free Software Foundation, Inc.
    Contributed by Joseph Myers <joseph@codesourcery.com>
                  Bernd Schmidt  <bernds@codesourcery.com>
 
@@ -2717,6 +2716,30 @@ tic6x_try_encode (tic6x_opcode_id id, tic6x_operand *operands,
          *fix_adda = FALSE;
          break;
 
+       case tic6x_coding_regpair_lsb:
+         switch (operands[opno].form)
+           {
+           case TIC6X_OP_REGPAIR:
+             value = operands[opno].value.reg.num;
+             break;
+
+           default:
+             abort ();
+           }
+         break;
+
+       case tic6x_coding_regpair_msb:
+         switch (operands[opno].form)
+           {
+           case TIC6X_OP_REGPAIR:
+             value = operands[opno].value.reg.num + 1;
+             break;
+
+           default:
+             abort ();
+           }
+         break;
+
        case tic6x_coding_reg:
          switch (operands[opno].form)
            {

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 37c9e87..e1c0481 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+       PR gas/15095
+       * gas/tic6x/insns-c674x.s: Add test cases for the newly generated
+       opcode.
+       * gas/tic6x/insns-c674x.d: Update expected disassembly.
+
 2013-03-15  Will Newton  <will.newton@linaro.org>
 
        * gas/arm/any-idiv.d: Expand *-*eabi test to cover *-*eabi*.

diff --git a/gas/testsuite/gas/tic6x/insns-c674x.d b/gas/testsuite/gas/tic6x/insns-c674x.d
index 236086c..9f8e162 100644 (file)
--- a/gas/testsuite/gas/tic6x/insns-c674x.d
+++ b/gas/testsuite/gas/tic6x/insns-c674x.d
@@ -17,7 +17,9 @@ Disassembly of section \.text:
 [0-9a-f]+[048c] <[^>]*> 070c835a[ \t]+abs2 \.L2 b3,b14
 [0-9a-f]+[048c] <[^>]*> 0cf0935a[ \t]+abs2 \.L2X a28,b25
 [0-9a-f]+[048c] <[^>]*> 0c180b20[ \t]+absdp \.S1 a7:a6,a25:a24
-[0-9a-f]+[048c] <[^>]*> c2080b22[ \t]+\[a0\] absdp \.S2 b3:b2,b5:b4
+[0-9a-f]+[048c] <[^>]*> 0c1ccb20[ \t]+absdp \.S1 a7:a6,a25:a24
+[0-9a-f]+[048c] <[^>]*> c20c4b22[ \t]+\[a0\] absdp \.S2 b3:b2,b5:b4
+[0-9a-f]+[048c] <[^>]*> 0c1feb20[ \t]+absdp \.S1 a7:a6,a25:a24
 [0-9a-f]+[048c] <[^>]*> 04240f20[ \t]+abssp \.S1 a9,a8
 [0-9a-f]+[048c] <[^>]*> 08481f20[ \t]+abssp \.S1X b18,a16
 [0-9a-f]+[048c] <[^>]*> 23800f22[ \t]+\[b0\] abssp \.S2 b0,b7
@@ -442,11 +444,17 @@ Disassembly of section \.text:
 [0-9a-f]+[048c] <[^>]*> 1325867a[ \t]+dpackx2 \.L2 b12,b9,b7:b6
 [0-9a-f]+[048c] <[^>]*> 1e00767a[ \t]+dpackx2 \.L2X b3,a0,b29:b28
 [0-9a-f]+[048c] <[^>]*> 01900118[ \t]+dpint \.L1 a5:a4,a3
-[0-9a-f]+[048c] <[^>]*> d190011a[ \t]+\[!a0\] dpint \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 01948118[ \t]+dpint \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> d194811a[ \t]+\[!a0\] dpint \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 0197e118[ \t]+dpint \.L1 a5:a4,a3
 [0-9a-f]+[048c] <[^>]*> 01900138[ \t]+dpsp \.L1 a5:a4,a3
-[0-9a-f]+[048c] <[^>]*> 3190013a[ \t]+\[!b0\] dpsp \.L2 b5:b4,b3
-[0-9a-f]+[048c] <[^>]*> 81900038[ \t]+\[a1\] dptrunc \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> 01948138[ \t]+dpsp \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> 3194813a[ \t]+\[!b0\] dpsp \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 0197e138[ \t]+dpsp \.L1 a5:a4,a3
 [0-9a-f]+[048c] <[^>]*> 0190003a[ \t]+dptrunc \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 81948038[ \t]+\[a1\] dptrunc \.L1 a5:a4,a3
+[0-9a-f]+[048c] <[^>]*> 0194803a[ \t]+dptrunc \.L2 b5:b4,b3
+[0-9a-f]+[048c] <[^>]*> 0197e03a[ \t]+dptrunc \.L2 b5:b4,b3
 [0-9a-f]+[048c] <[^>]*> 05141f48[ \t]+ext \.S1 a5,0,31,a10
 [0-9a-f]+[048c] <[^>]*> 42abe04a[ \t]+\[b1\] ext \.S2 b10,31,0,b5
 [0-9a-f]+[048c] <[^>]*> 9a9dcbe0[ \t]+\[!a1\] ext \.S1 a7,a14,a21
@@ -1033,7 +1041,9 @@ Disassembly of section \.text:
 [0-9a-f]+[048c] <[^>]*> 0b8aad1a[ \t]+packl4 \.L2 b21,b2,b23
 [0-9a-f]+[048c] <[^>]*> 64c33d1a[ \t]+\[b2\] packl4 \.L2X b25,a16,b9
 [0-9a-f]+[048c] <[^>]*> 03100b60[ \t]+rcpdp \.S1 a5:a4,a7:a6
-[0-9a-f]+[048c] <[^>]*> b5200b62[ \t]+\[!a2\] rcpdp \.S2 b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 03148b60[ \t]+rcpdp \.S1 a5:a4,a7:a6
+[0-9a-f]+[048c] <[^>]*> b5250b62[ \t]+\[!a2\] rcpdp \.S2 b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 0317eb60[ \t]+rcpdp \.S1 a5:a4,a7:a6
 [0-9a-f]+[048c] <[^>]*> 00800f60[ \t]+rcpsp \.S1 a0,a1
 [0-9a-f]+[048c] <[^>]*> 71881f60[ \t]+\[!b2\] rcpsp \.S1X b2,a3
 [0-9a-f]+[048c] <[^>]*> c2900f62[ \t]+\[a0\] rcpsp \.S2 b4,b5
@@ -1052,7 +1062,9 @@ Disassembly of section \.text:
 [0-9a-f]+[048c] <[^>]*> 14a0eef2[ \t]+rpack2 \.S2 b7,b8,b9
 [0-9a-f]+[048c] <[^>]*> 162d5ef2[ \t]+rpack2 \.S2X b10,a11,b12
 [0-9a-f]+[048c] <[^>]*> 03100ba0[ \t]+rsqrdp \.S1 a5:a4,a7:a6
-[0-9a-f]+[048c] <[^>]*> 45200ba2[ \t]+\[b1\] rsqrdp \.S2 b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 03148ba0[ \t]+rsqrdp \.S1 a5:a4,a7:a6
+[0-9a-f]+[048c] <[^>]*> 45250ba2[ \t]+\[b1\] rsqrdp \.S2 b9:b8,b11:b10
+[0-9a-f]+[048c] <[^>]*> 0317eba0[ \t]+rsqrdp \.S1 a5:a4,a7:a6
 [0-9a-f]+[048c] <[^>]*> 00800fa0[ \t]+rsqrsp \.S1 a0,a1
 [0-9a-f]+[048c] <[^>]*> 91881fa0[ \t]+\[!a1\] rsqrsp \.S1X b2,a3
 [0-9a-f]+[048c] <[^>]*> 52900fa2[ \t]+\[!b1\] rsqrsp \.S2 b4,b5

diff --git a/gas/testsuite/gas/tic6x/insns-c674x.s b/gas/testsuite/gas/tic6x/insns-c674x.s
index 1d02e7e..33ec5da 100644 (file)
--- a/gas/testsuite/gas/tic6x/insns-c674x.s
+++ b/gas/testsuite/gas/tic6x/insns-c674x.s
@@ -13,8 +13,10 @@ f:
        [a2] abs2 .L1X b23,a5
        abs2 .L2 b3,b14
        abs2 .L2X a28,b25
+       .word 0x0c180b20
        absdp .S1 a7:a6,a25:a24
        [a0] absdp .S2 b3:b2,b5:b4
+       .word 0x0c1feb20
        abssp .S1 a9,a8
        abssp .S1X b18,a16
        [b0] abssp .S2 b0,b7
@@ -438,12 +440,18 @@ f:
        dpackx2 .L1X a21,b18,a15:a14
        dpackx2 .L2 b12,b9,b7:b6
        dpackx2 .L2X b3,a0,b29:b28
+       .word 0x01900118
        dpint .L1 a5:a4,a3
        [!a0] dpint .L2 b5:b4,b3
+       .word 0x0197e118
+       .word 0x01900138
        dpsp .L1 a5:a4,a3
        [!b0] dpsp .L2 b5:b4,b3
+       .word 0x0197e138
+       .word 0x0190003a
        [a1] dptrunc .L1 a5:a4,a3
        dptrunc .L2 b5:b4,b3
+       .word 0x0197e03a
        ext .S1 a5,0,31,a10
        [b1] ext .S2 b10,31,0,b5
        [!a1] ext .S1 a7,a14,a21
@@ -1029,8 +1037,10 @@ f:
        packl4 .L1X a5,b8,a13
        packl4 .L2 b21,b2,b23
        [b2] packl4 .L2X b25,a16,b9
+       .word 0x03100b60
        rcpdp .S1 a5:a4,a7:a6
        [!a2] rcpdp .S2 b9:b8,b11:b10
+       .word 0x0317eb60
        rcpsp .S1 a0,a1
        [!b2] rcpsp .S1X b2,a3
        [a0] rcpsp .S2 b4,b5
@@ -1048,8 +1058,10 @@ f:
        rpack2 .S1X a4,b5,a6
        rpack2 .S2 b7,b8,b9
        rpack2 .S2X b10,a11,b12
+       .word 0x03100ba0
        rsqrdp .S1 a5:a4,a7:a6
        [b1] rsqrdp .S2 b9:b8,b11:b10
+       .word 0x0317eba0
        rsqrsp .S1 a0,a1
        [!a1] rsqrsp .S1X b2,a3
        [!b1] rsqrsp .S2 b4,b5

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index a46900a..69d0859 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,13 @@
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+       PR gas/15095
+       * tic6x.h (enum tic6x_coding_method): Add
+       tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
+       separately the msb and lsb of a register pair.  This is needed to
+       encode the opcodes in the same way as TI assembler does.
+       * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
+       and rsqrdp opcodes to use the new field coding types.
+
 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * arm.h (CRC_EXT_ARMV8): New constant.

diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h
index 45e26fb..abebd3c 100644 (file)
--- a/include/opcode/tic6x-opcode-table.h
+++ b/include/opcode/tic6x-opcode-table.h
@@ -1,6 +1,5 @@
 /* TI C6X opcode table.
-   Copyright 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright 2010-2013 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -129,9 +128,10 @@ INSN(abs2, l, unary, 1cycle, C64X, 0,
          ENC(dst, reg, 1)))
 
 INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x2c), FIX(x, 0)),
      OP2(ORREGD1, OWREGD12),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+         ENC(dst, reg, 1)))
 
 INSN(abssp, s, unary, 1cycle, C67X, 0,
      FIX1(FIX(op, 0)),
@@ -916,19 +916,22 @@ INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
          ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x8), FIX(x, 0)),
      OP2(ORREGD1, OWREG4),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+         ENC(dst, reg, 1)))
 
 INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x9), FIX(x, 0)),
      OP2(ORREGD1, OWREG4),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+         ENC(dst, reg, 1)))
 
 INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x1), FIX(x, 0)),
      OP2(ORREGD1, OWREG4),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+         ENC(dst, reg, 1)))
 
 INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
      FIX1(FIX(op, 0x1)),
@@ -1617,9 +1620,10 @@ INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0,
          ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x2d), FIX(x, 0)),
      OP2(ORREGD1, OWREGD12),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+         ENC(dst, reg, 1)))
 
 INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0,
      FIX2(FIX(op, 0x3d), FIX(src1, 0)),
@@ -1677,9 +1681,10 @@ INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0,
          ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x2e), FIX(x, 0)),
      OP2(ORREGD1, OWREGD12),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+         ENC(dst, reg, 1)))
 
 INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0,
      FIX2(FIX(op, 0x3e), FIX(src1, 0)),

diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h
index 2a7a246..168f660 100644 (file)
--- a/include/opcode/tic6x.h
+++ b/include/opcode/tic6x.h
@@ -1,6 +1,5 @@
 /* TI C6X opcode information.
-   Copyright 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright 2010-2013 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -380,6 +379,12 @@ typedef enum
        the field.  When applied to a memory reference, encode the base
        register.  */
     tic6x_coding_reg,
+    /* Encode the register-pair's lsb (even register) for instructions
+       that use src1 as port for loading lsb of double-precision
+       operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp).  */
+    tic6x_coding_regpair_lsb,
+    /* Encode the register-pair's msb (odd register), see above.  */ 
+    tic6x_coding_regpair_msb,
     /* Store 0 for register B14, 1 for register B15.  When applied to
        a memory reference, encode the base register.  */
     tic6x_coding_areg,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 66556f1..a678a70 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,15 @@
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+       PR gas/15095
+       * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
+       individual msb and lsb halves in src1 & src2 fields.  Discard the
+       src1 (lsb) value and only use src2 (msb), discarding bit 0, to
+       follow what Ti SDK does in that case as any value in the src1
+       field yields the same output with SDK disassembler.
+
 2013-03-12  Michael Eager <eager@eagercon.com>
 
-       * opcodes/mips-dis.c (print_insn_args): Modify def of reg. 
+       * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 
 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 

diff --git a/opcodes/tic6x-dis.c b/opcodes/tic6x-dis.c
index 05626df..73ac2e0 100644 (file)
--- a/opcodes/tic6x-dis.c
+++ b/opcodes/tic6x-dis.c
@@ -1,6 +1,5 @@
 /* TI C6X disassembler.
-   Copyright 2010
-   Free Software Foundation, Inc.
+   Copyright 2010-2013 Free Software Foundation, Inc.
    Contributed by Joseph Myers <joseph@codesourcery.com>
                  Bernd Schmidt  <bernds@codesourcery.com>
 
@@ -632,6 +631,15 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info)
                  operands_addresses[op_num] = fp_addr + signed_fld_val;
                  break;
 
+               case tic6x_coding_regpair_msb:
+                 if (opc->operand_info[op_num].form != tic6x_operand_regpair)
+                   abort ();
+                 operands_text[op_num] = TRUE;
+                 snprintf (operands[op_num], 24, "%c%u:%c%u",
+                           (func_unit_side == 2 ? 'b' : 'a'), (fld_val | 0x1),
+                           (func_unit_side == 2 ? 'b' : 'a'), (fld_val | 0x1) - 1);
+                 break;
+
                case tic6x_coding_reg_shift:
                  fld_val <<= 1;
                  /* Fall through.  */