Merge tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel...
authorArnd Bergmann <arnd@arndb.de>
Thu, 24 Feb 2022 21:46:59 +0000 (22:46 +0100)
committerArnd Bergmann <arnd@arndb.de>
Thu, 24 Feb 2022 21:46:59 +0000 (22:46 +0100)
Fix the display-port-sound on Gru devices, DDR voltage on the Quartz-A
board, fix emmc signal-integrity and usb OTG mode on rk3399-puma as well
as a number of dtschema fixes to make the reduce the number of errors.

* tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: fix a typo on rk3288 crypto-controller
  ARM: dts: rockchip: reorder rk322x hmdi clocks
  arm64: dts: rockchip: reorder rk3399 hdmi clocks
  arm64: dts: rockchip: align pl330 node name with dtschema
  arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity
  arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage
  arm64: dts: rockchip: Switch RK3399-Gru DP to SPDIF output
  arm64: dts: rockchip: fix rk3399-puma-haikou USB OTG mode
  arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568
  arm64: dts: rockchip: fix dma-controller node names on rk356x

Link: https://lore.kernel.org/r/1973741.CViHJPHrxy@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/boot/dts/rk322x.dtsi
arch/arm/boot/dts/rk3288.dtsi
arch/arm64/boot/dts/rockchip/px30.dtsi
arch/arm64/boot/dts/rockchip/rk3328.dtsi
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
arch/arm64/boot/dts/rockchip/rk3568.dtsi
arch/arm64/boot/dts/rockchip/rk356x.dtsi

index 8eed9e3a92e901b6c2769e38224423de1be950da..5868eb512f69fef83251fcf56138ba125cdfa1b9 100644 (file)
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                assigned-clocks = <&cru SCLK_HDMI_PHY>;
                assigned-clock-parents = <&hdmi_phy>;
-               clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
-               clock-names = "isfr", "iahb", "cec";
+               clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+               clock-names = "iahb", "isfr", "cec";
                pinctrl-names = "default";
                pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
                resets = <&cru SRST_HDMI_P>;
index aaaa61875701d916bd75ab032c655bf208d3b3df..45a9d9b908d2a1a3ecb15340383f1c744ef62724 100644 (file)
                status = "disabled";
        };
 
-       crypto: cypto-controller@ff8a0000 {
+       crypto: crypto@ff8a0000 {
                compatible = "rockchip,rk3288-crypto";
                reg = <0x0 0xff8a0000 0x0 0x4000>;
                interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
index f972704dfe7abf27585bda276194b1875e8569af..56dfbb2e2fa66440af6f57b608e8f19a3e6b7d8d 100644 (file)
                clock-names = "pclk", "timer";
        };
 
-       dmac: dmac@ff240000 {
+       dmac: dma-controller@ff240000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x0 0xff240000 0x0 0x4000>;
                interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
index 39db0b85b4da2a730a9982c47452406886d33f06..b822533dc7f19e73993bbf399e0b8e243755727c 100644 (file)
                status = "disabled";
        };
 
-       dmac: dmac@ff1f0000 {
+       dmac: dma-controller@ff1f0000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x0 0xff1f0000 0x0 0x4000>;
                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
index 45a5ae5d2027f858f60bb6abb0746c00de82de10..162f08bca0d40618176531eecdff1ad159c085c0 100644 (file)
 
        sound: sound {
                compatible = "rockchip,rk3399-gru-sound";
-               rockchip,cpu = <&i2s0 &i2s2>;
+               rockchip,cpu = <&i2s0 &spdif>;
        };
 };
 
@@ -437,10 +437,6 @@ ap_i2c_audio: &i2c8 {
        status = "okay";
 };
 
-&i2s2 {
-       status = "okay";
-};
-
 &io_domains {
        status = "okay";
 
@@ -537,6 +533,17 @@ ap_i2c_audio: &i2c8 {
        vqmmc-supply = <&ppvar_sd_card_io>;
 };
 
+&spdif {
+       status = "okay";
+
+       /*
+        * SPDIF is routed internally to DP; we either don't use these pins, or
+        * mux them to something else.
+        */
+       /delete-property/ pinctrl-0;
+       /delete-property/ pinctrl-names;
+};
+
 &spi1 {
        status = "okay";
 
index 292bb7e80cf35dab9564fb77d4dee224743ec066..3ae5d727e36745425288311d14073aefe1117f25 100644 (file)
 
 &usbdrd_dwc3_0 {
        dr_mode = "otg";
+       extcon = <&extcon_usb3>;
        status = "okay";
 };
 
index fb67db4619ea07087d55bef9d711bc8c34aa292b..08fa00364b42f0f4a509cf0c5613ebd79fe56a9d 100644 (file)
                };
        };
 
+       extcon_usb3: extcon-usb3 {
+               compatible = "linux,extcon-usb-gpio";
+               id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&usb3_id>;
+       };
+
        clkin_gmac: external-gmac-clock {
                compatible = "fixed-clock";
                clock-frequency = <125000000>;
                          <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };
+
+       usb3 {
+               usb3_id: usb3-id {
+                       rockchip,pins =
+                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
 };
 
 &sdhci {
+       /*
+        * Signal integrity isn't great at 200MHz but 100MHz has proven stable
+        * enough.
+        */
+       max-frequency = <100000000>;
+
        bus-width = <8>;
        mmc-hs400-1_8v;
        mmc-hs400-enhanced-strobe;
index d3cdf6f42a30367d7255cd6ce7907b551a081f70..080457a68e3c70e99a8fc517e3a24290463ba6dc 100644 (file)
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&cru PCLK_HDMI_CTRL>,
                         <&cru SCLK_HDMI_SFR>,
-                        <&cru PLL_VPLL>,
+                        <&cru SCLK_HDMI_CEC>,
                         <&cru PCLK_VIO_GRF>,
-                        <&cru SCLK_HDMI_CEC>;
-               clock-names = "iahb", "isfr", "vpll", "grf", "cec";
+                        <&cru PLL_VPLL>;
+               clock-names = "iahb", "isfr", "cec", "grf", "vpll";
                power-domains = <&power RK3399_PD_HDCP>;
                reg-io-width = <4>;
                rockchip,grf = <&grf>;
index 166399b7f13f05b6d8c04c68bc463fcd2731d501..d9eb92d5909907cc219992f3a21959763b4ba6a6 100644 (file)
                        vcc_ddr: DCDC_REG3 {
                                regulator-always-on;
                                regulator-boot-on;
-                               regulator-min-microvolt = <1100000>;
-                               regulator-max-microvolt = <1100000>;
                                regulator-initial-mode = <0x2>;
                                regulator-name = "vcc_ddr";
                                regulator-state-mem {
index 2fd313a295f8aaa1d5c7a8b1250fc428513baa88..d91df1cde73631947d2ad49b01f31e0ed0229c27 100644 (file)
                clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
                         <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
                         <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
-                        <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
-                        <&cru PCLK_XPCS>;
+                        <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
                clock-names = "stmmaceth", "mac_clk_rx",
                              "mac_clk_tx", "clk_mac_refout",
                              "aclk_mac", "pclk_mac",
-                             "clk_mac_speed", "ptp_ref",
-                             "pclk_xpcs";
+                             "clk_mac_speed", "ptp_ref";
                resets = <&cru SRST_A_GMAC0>;
                reset-names = "stmmaceth";
                rockchip,grf = <&grf>;
index a68033a239750454b554ef2f9be3c8ad23204c68..8ccce54ee8e728e9cef67ed1f85f7d14b54f25cc 100644 (file)
                status = "disabled";
        };
 
-       dmac0: dmac@fe530000 {
+       dmac0: dma-controller@fe530000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x0 0xfe530000 0x0 0x4000>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                #dma-cells = <1>;
        };
 
-       dmac1: dmac@fe550000 {
+       dmac1: dma-controller@fe550000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x0 0xfe550000 0x0 0x4000>;
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,