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clk: rockchip: export HDMIPHY clock on rk3228
author
Heiko Stuebner
<heiko@sntech.de>
Fri, 14 Jun 2019 08:59:48 +0000
(10:59 +0200)
committer
Heiko Stuebner
<heiko@sntech.de>
Thu, 27 Jun 2019 09:02:28 +0000
(11:02 +0200)
Export the hdmiphy clock mux via the newly added clock-id.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Justin Swartz <justin.swartz@risingedge.co.za>
drivers/clk/rockchip/clk-rk3228.c
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diff --git
a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index
0801da8
..
68bf4f8
100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3228.c
+++ b/
drivers/clk/rockchip/clk-rk3228.c
@@
-256,7
+256,7
@@
static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(4), 0, GFLAGS),
/* PD_MISC */
- MUX(
0
, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
+ MUX(
SCLK_HDMI_PHY
, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 13, 1, MFLAGS),
MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 14, 1, MFLAGS),