drm/amdgpu: don't modify num_doorbells for mes

This patch removes the check and change in num_kernel_doorbells
for MES, which is not being used anywhere by MES code.

V2: Fixed checkpatch warnings.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Christian Koenig <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
index 31db526..5c0d3ce 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
@@ -140,25 +140,21 @@ int amdgpu_doorbell_init(struct amdgpu_device *adev)
        adev->doorbell.base = pci_resource_start(adev->pdev, 2);
        adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 
-       if (adev->enable_mes) {
-               adev->doorbell.num_kernel_doorbells =
-                       adev->doorbell.size / sizeof(u32);
-       } else {
-               adev->doorbell.num_kernel_doorbells =
-                       min_t(u32, adev->doorbell.size / sizeof(u32),
-                             adev->doorbell_index.max_assignment+1);
-               if (adev->doorbell.num_kernel_doorbells == 0)
-                       return -EINVAL;
-
-               /* For Vega, reserve and map two pages on doorbell BAR since SDMA
-                * paging queue doorbell use the second page. The
-                * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
-                * doorbells are in the first page. So with paging queue enabled,
-                * the max num_kernel_doorbells should + 1 page (0x400 in dword)
-                */
-               if (adev->asic_type >= CHIP_VEGA10)
-                       adev->doorbell.num_kernel_doorbells += 0x400;
-       }
+       adev->doorbell.num_kernel_doorbells =
+               min_t(u32, adev->doorbell.size / sizeof(u32),
+                     adev->doorbell_index.max_assignment + 1);
+       if (adev->doorbell.num_kernel_doorbells == 0)
+               return -EINVAL;
+
+       /*
+        * For Vega, reserve and map two pages on doorbell BAR since SDMA
+        * paging queue doorbell use the second page. The
+        * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
+        * doorbells are in the first page. So with paging queue enabled,
+        * the max num_kernel_doorbells should + 1 page (0x400 in dword)
+        */
+       if (adev->asic_type >= CHIP_VEGA10)
+               adev->doorbell.num_kernel_doorbells += 0x400;
 
        adev->doorbell.ptr = ioremap(adev->doorbell.base,
                                     adev->doorbell.num_kernel_doorbells *