tty/serial: Migrate ip22zilog to use has_sysrq
authorDmitry Safonov <dima@arista.com>
Fri, 13 Dec 2019 00:06:19 +0000 (00:06 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 18 Dec 2019 14:04:50 +0000 (15:04 +0100)
The SUPPORT_SYSRQ ifdeffery is not nice as:
- May create misunderstanding about sizeof(struct uart_port) between
  different objects
- Prevents moving functions from serial_core.h
- Reduces readability (well, it's ifdeffery - it's hard to follow)

In order to remove SUPPORT_SYSRQ, has_sysrq variable has been added.
Initialise it in driver's probe and remove ifdeffery.

Signed-off-by: Dmitry Safonov <dima@arista.com>
Link: https://lore.kernel.org/r/20191213000657.931618-21-dima@arista.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/ip22zilog.c

index 8c81073..86fff69 100644 (file)
 #include <asm/sgi/hpc3.h>
 #include <asm/sgi/ip22.h>
 
-#if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-#define SUPPORT_SYSRQ
-#endif
-
 #include <linux/serial_core.h>
 
 #include "ip22zilog.h"
@@ -1080,6 +1076,7 @@ static struct uart_driver ip22zilog_reg = {
 
 static void __init ip22zilog_prepare(void)
 {
+       unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE);
        struct uart_ip22zilog_port *up;
        struct zilog_layout *rp;
        int channel, chip;
@@ -1115,6 +1112,7 @@ static void __init ip22zilog_prepare(void)
                up[(chip * 2) + 0].port.irq = zilog_irq;
                up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
                up[(chip * 2) + 0].port.fifosize = 1;
+               up[(chip * 2) + 0].port.has_sysrq = sysrq_on;
                up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
                up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
                up[(chip * 2) + 0].port.flags = 0;
@@ -1126,6 +1124,7 @@ static void __init ip22zilog_prepare(void)
                up[(chip * 2) + 1].port.irq = zilog_irq;
                up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
                up[(chip * 2) + 1].port.fifosize = 1;
+               up[(chip * 2) + 1].port.has_sysrq = sysrq_on;
                up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
                up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
                up[(chip * 2) + 1].port.line = (chip * 2) + 1;