Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and 'clk...

 - Support for Versa 5P49V60 clks

* clk-cleanup:
  clk: rs9: Drop unused pin_xin field
  clk: sprd: Add dependency for SPRD_UMS512_CLK
  clk: ralink: fix 'mt7621_gate_is_enabled()' function
  dt-bindings: clock: remove stih416 bindings
  drivers/clk: Remove "select SRCU"

* clk-bindings:
  dt-bindings: clock: qcom,sm8450-camcc: constrain required-opps
  dt-bindings: clock: imx8m-clock: correct i.MX8MQ node name

* clk-renesas:
  clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
  clk: renesas: r8a779g0: Add CAN-FD clocks
  clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC
  clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC
  clk: renesas: r8a779g0: Add custom clock for PLL2
  clk: renesas: cpg-mssr: Remove superfluous check in resume code
  clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence
  clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed
  clk: renesas: r9a07g044: Add clock and reset entries for CRU
  clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
  clk: renesas: r9a09g011: Add USB clock and reset entries
  clk: renesas: r9a09g011: Add TIM clock and reset entries
  clk: renesas: r8a779g0: Add display related clocks
  clk: renesas: rcar-gen4: Restore PLL enum sort order
  clk: renesas: r8a779g0: Fix OSC predividers
  clk: renesas: r9a09g011: Add PWM clock and reset entries

* clk-versa:
  dt-bindings: clock: versaclock5: Document 5P49V60 compatible string
  clk: vc5: Add support for 5P49V60
  clk: vc5: Use `clamp()` to restrict PLL range

* clk-amlogic:
  clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
  clk: meson: sclk-div: switch from .round_rate to .determine_rate
  clk: meson: dualdiv: switch from .round_rate to .determine_rate
  clk: meson: mpll: Switch from .round_rate to .determine_rate