drm/amd/display: Add DCN3 Support in DM (v2)

Handle DCN3 in amdgpu_dm

v2: fix num_pkrs handling

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 435bfae..c64beb2 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -94,6 +94,10 @@
 
 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
+#endif
 
 #define FIRMWARE_RAVEN_DMCU            "amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1070,6 +1074,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
        case CHIP_NAVI10:
        case CHIP_NAVI14:
        case CHIP_RENOIR:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       case CHIP_SIENNA_CICHLID:
+#endif
                return 0;
        case CHIP_NAVI12:
                fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1166,6 +1173,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
                dmub_asic = DMUB_ASIC_DCN21;
                fw_name_dmub = FIRMWARE_RENOIR_DMUB;
                break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       case CHIP_SIENNA_CICHLID:
+               dmub_asic = DMUB_ASIC_DCN30;
+               fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
+               break;
+#endif
 
        default:
                /* ASIC doesn't support DMUB. */
@@ -3205,6 +3218,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
        case CHIP_NAVI10:
        case CHIP_NAVI14:
        case CHIP_RENOIR:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       case CHIP_SIENNA_CICHLID:
+#endif
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -3359,6 +3375,9 @@ static int dm_early_init(void *handle)
 #endif
        case CHIP_NAVI10:
        case CHIP_NAVI12:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       case CHIP_SIENNA_CICHLID:
+#endif
                adev->mode_info.num_crtc = 6;
                adev->mode_info.num_hpd = 6;
                adev->mode_info.num_dig = 6;
@@ -3679,6 +3698,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
            adev->asic_type == CHIP_NAVI10 ||
            adev->asic_type == CHIP_NAVI14 ||
            adev->asic_type == CHIP_NAVI12 ||
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+               adev->asic_type == CHIP_SIENNA_CICHLID ||
+#endif
            adev->asic_type == CHIP_RENOIR ||
            adev->asic_type == CHIP_RAVEN) {
                /* Fill GFX9 params */
@@ -3698,6 +3720,11 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
                        AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
                tiling_info->gfx9.shaderEnable = 1;
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+               if (adev->asic_type == CHIP_SIENNA_CICHLID)
+                       tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
+
+#endif
                ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
                                                plane_size, tiling_info,
                                                tiling_flags, dcc, address,

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b086d5c..d839eb1 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -627,3 +627,23 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 {
        /* TODO: something */
 }
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+
+void *dm_helpers_allocate_gpu_mem(
+               struct dc_context *ctx,
+               enum dc_gpu_mem_alloc_type type,
+               size_t size,
+               long long *addr)
+{
+       // TODO
+       return NULL;
+}
+
+void dm_helpers_free_gpu_mem(
+               struct dc_context *ctx,
+               enum dc_gpu_mem_alloc_type type,
+               void *pvMem)
+{
+       // TODO
+}
+#endif

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 9517547..b7a8c71 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -390,6 +390,7 @@ union dc_tiling_info {
                bool meta_linear;
                bool rb_aligned;
                bool pipe_aligned;
+               unsigned int num_pkrs;
        } gfx9;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index c726fb0..d7b9d31 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -887,6 +887,15 @@ struct dsc_dec_dpcd_caps {
        uint32_t branch_max_line_width;
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+enum dc_gpu_mem_alloc_type {
+       DC_MEM_ALLOC_TYPE_GART,
+       DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+       DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
+       DC_MEM_ALLOC_TYPE_AGP
+};
+
+#endif
 enum dc_psr_version {
        DC_PSR_VERSION_1                        = 0,
        DC_PSR_VERSION_UNSUPPORTED              = 0xFFFFFFFF,

diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 8bde1d6..b2cc2bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -35,6 +35,29 @@
 
 struct dp_mst_stream_allocation_table;
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+/*
+ * Allocate memory accessible by the GPU
+ *
+ * frame buffer allocations must be aligned to a 4096-byte boundary
+ *
+ * Returns virtual address, sets addr to physical address
+ */
+void *dm_helpers_allocate_gpu_mem(
+               struct dc_context *ctx,
+               enum dc_gpu_mem_alloc_type type,
+               size_t size,
+               long long *addr);
+
+/*
+ * Free the GPU-accessible memory at the virtual address pvMem
+ */
+void dm_helpers_free_gpu_mem(
+               struct dc_context *ctx,
+               enum dc_gpu_mem_alloc_type type,
+               void *pvMem);
+
+#endif
 enum dc_edid_status dm_helpers_parse_edid_caps(
        struct dc_context *ctx,
        const struct dc_edid *edid,