[NFC][InstCombine] Add shift amount reassociation in bittest tests (PR42399)

https://bugs.llvm.org/show_bug.cgi?id=42399
https://rise4fun.com/Alive/kBb
https://rise4fun.com/Alive/1SB

llvm-svn: 364430

diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
new file mode 100644 (file)
index 0000000..7cd340e
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
@@ -0,0 +1,420 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; Given pattern:
+;   icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 0
+; we should move shifts to the same hand of 'and', i.e. e.g. rewrite as
+;   icmp eq/ne (and (((x shift Q) shift K), y)), 0
+; We are only interested in opposite logical shifts here.
+
+; Basic scalar test with constants
+
+define i1 @t0_const_lshr_shl_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: @t0_const_lshr_shl_ne(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], 1
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, 1
+  %t1 = shl i32 %y, 1
+  %t2 = and i32 %t1, %t0
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t1_const_shl_lshr_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: @t1_const_shl_lshr_ne(
+; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[Y:%.*]], 1
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = shl i32 %x, 1
+  %t1 = lshr i32 %y, 1
+  %t2 = and i32 %t1, %t0
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+
+; We are ok with 'eq' predicate too.
+define i1 @t2_const_lshr_shl_eq(i32 %x, i32 %y) {
+; CHECK-LABEL: @t2_const_lshr_shl_eq(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], 1
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp eq i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, 1
+  %t1 = shl i32 %y, 1
+  %t2 = and i32 %t1, %t0
+  %t3 = icmp eq i32 %t2, 0
+  ret i1 %t3
+}
+
+; Basic scalar test with constants after folding
+
+define i1 @t3_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
+; CHECK-LABEL: @t3_const_after_fold_lshr_shl_ne(
+; CHECK-NEXT:    [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT:    [[T2:%.*]] = add i32 [[LEN]], -1
+; CHECK-NEXT:    [[T3:%.*]] = shl i32 [[Y:%.*]], [[T2]]
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp ne i32 [[T4]], 0
+; CHECK-NEXT:    ret i1 [[T5]]
+;
+  %t0 = sub i32 32, %len
+  %t1 = lshr i32 %x, %t0
+  %t2 = add i32 %len, -1
+  %t3 = shl i32 %y, %t2
+  %t4 = and i32 %t1, %t3
+  %t5 = icmp ne i32 %t4, 0
+  ret i1 %t5
+}
+define i1 @t4_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
+; CHECK-LABEL: @t4_const_after_fold_lshr_shl_ne(
+; CHECK-NEXT:    [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT:    [[T2:%.*]] = add i32 [[LEN]], -1
+; CHECK-NEXT:    [[T3:%.*]] = lshr i32 [[Y:%.*]], [[T2]]
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp ne i32 [[T4]], 0
+; CHECK-NEXT:    ret i1 [[T5]]
+;
+  %t0 = sub i32 32, %len
+  %t1 = shl i32 %x, %t0
+  %t2 = add i32 %len, -1
+  %t3 = lshr i32 %y, %t2
+  %t4 = and i32 %t1, %t3
+  %t5 = icmp ne i32 %t4, 0
+  ret i1 %t5
+}
+
+; Completely variable shift amounts
+
+define i1 @t5_const_lshr_shl_ne(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
+; CHECK-LABEL: @t5_const_lshr_shl_ne(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, %shamt0
+  %t1 = shl i32 %y, %shamt1
+  %t2 = and i32 %t1, %t0
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t6_const_shl_lshr_ne(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
+; CHECK-LABEL: @t6_const_shl_lshr_ne(
+; CHECK-NEXT:    [[T0:%.*]] = shl i32 [[X:%.*]], [[SHAMT0:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[Y:%.*]], [[SHAMT1:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = shl i32 %x, %shamt0
+  %t1 = lshr i32 %y, %shamt1
+  %t2 = and i32 %t1, %t0
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+
+; Very basic vector tests
+
+define <2 x i1> @t7_const_lshr_shl_ne_vec_splat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t7_const_lshr_shl_ne_vec_splat(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[T3]]
+;
+  %t0 = lshr <2 x i32> %x, <i32 1, i32 1>
+  %t1 = shl <2 x i32> %y, <i32 1, i32 1>
+  %t2 = and <2 x i32> %t1, %t0
+  %t3 = icmp ne <2 x i32> %t2, <i32 0, i32 0>
+  ret <2 x i1> %t3
+}
+define <2 x i1> @t8_const_lshr_shl_ne_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t8_const_lshr_shl_ne_vec_nonsplat(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 1, i32 2>
+; CHECK-NEXT:    [[T1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 3, i32 4>
+; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[T3]]
+;
+  %t0 = lshr <2 x i32> %x, <i32 1, i32 2>
+  %t1 = shl <2 x i32> %y, <i32 3, i32 4>
+  %t2 = and <2 x i32> %t1, %t0
+  %t3 = icmp ne <2 x i32> %t2, <i32 0, i32 0>
+  ret <2 x i1> %t3
+}
+define <3 x i1> @t9_const_lshr_shl_ne_vec_undef0(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t9_const_lshr_shl_ne_vec_undef0(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 0, i32 0>
+  ret <3 x i1> %t3
+}
+define <3 x i1> @t10_const_lshr_shl_ne_vec_undef1(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t10_const_lshr_shl_ne_vec_undef1(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 0, i32 0>
+  ret <3 x i1> %t3
+}
+define <3 x i1> @t11_const_lshr_shl_ne_vec_undef2(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t11_const_lshr_shl_ne_vec_undef2(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %t3
+}
+define <3 x i1> @t12_const_lshr_shl_ne_vec_undef3(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t12_const_lshr_shl_ne_vec_undef3(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 0, i32 0>
+  ret <3 x i1> %t3
+}
+define <3 x i1> @t13_const_lshr_shl_ne_vec_undef4(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t13_const_lshr_shl_ne_vec_undef4(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %t3
+}
+define <3 x i1> @t14_const_lshr_shl_ne_vec_undef5(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t14_const_lshr_shl_ne_vec_undef5(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %t3
+}
+define <3 x i1> @t15_const_lshr_shl_ne_vec_undef6(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t15_const_lshr_shl_ne_vec_undef6(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[T3]]
+;
+  %t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
+  %t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
+  %t2 = and <3 x i32> %t1, %t0
+  %t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %t3
+}
+
+; One-use tests
+
+declare void @use32(i32)
+
+define i1 @t16_const_oneuse0(i32 %x, i32 %y) {
+; CHECK-LABEL: @t16_const_oneuse0(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], 1
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, 1
+  %t1 = shl i32 %y, 1
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t17_const_oneuse1(i32 %x, i32 %y) {
+; CHECK-LABEL: @t17_const_oneuse1(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], 1
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, 1
+  call void @use32(i32 %t0)
+  %t1 = shl i32 %y, 1
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t18_const_oneuse2(i32 %x, i32 %y) {
+; CHECK-LABEL: @t18_const_oneuse2(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], 1
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, 1
+  %t1 = shl i32 %y, 1
+  call void @use32(i32 %t1)
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t19_const_oneuse2(i32 %x, i32 %y) {
+; CHECK-LABEL: @t19_const_oneuse2(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], 1
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, 1
+  call void @use32(i32 %t0)
+  %t1 = shl i32 %y, 1
+  call void @use32(i32 %t1)
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+
+define i1 @t17_variable_oneuse0(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
+; CHECK-LABEL: @t17_variable_oneuse0(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, %shamt0
+  %t1 = shl i32 %y, %shamt1
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t18_variable_oneuse1(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
+; CHECK-LABEL: @t18_variable_oneuse1(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, %shamt0
+  call void @use32(i32 %t0)
+  %t1 = shl i32 %y, %shamt1
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t19_variable_oneuse2(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
+; CHECK-LABEL: @t19_variable_oneuse2(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, %shamt0
+  %t1 = shl i32 %y, %shamt1
+  call void @use32(i32 %t1)
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+define i1 @t20_variable_oneuse2(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
+; CHECK-LABEL: @t20_variable_oneuse2(
+; CHECK-NEXT:    [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
+; CHECK-NEXT:    call void @use32(i32 [[T0]])
+; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
+; CHECK-NEXT:    call void @use32(i32 [[T1]])
+; CHECK-NEXT:    [[T2:%.*]] = and i32 [[T1]], [[T0]]
+; CHECK-NEXT:    call void @use32(i32 [[T2]])
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 0
+; CHECK-NEXT:    ret i1 [[T3]]
+;
+  %t0 = lshr i32 %x, %shamt0
+  call void @use32(i32 %t0)
+  %t1 = shl i32 %y, %shamt1
+  call void @use32(i32 %t1)
+  %t2 = and i32 %t1, %t0
+  call void @use32(i32 %t2)
+  %t3 = icmp ne i32 %t2, 0
+  ret i1 %t3
+}
+
+; Negative tests
+define <2 x i1> @n20_overshift(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @n20_overshift(
+; CHECK-NEXT:    [[T0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 15, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 17, i32 1>
+; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[T1]], [[T0]]
+; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[T3]]
+;
+  %t0 = lshr <2 x i32> %x, <i32 15, i32 1>
+  %t1 = shl <2 x i32> %y, <i32 17, i32 1>
+  %t2 = and <2 x i32> %t1, %t0
+  %t3 = icmp ne <2 x i32> %t2, <i32 0, i32 0>
+  ret <2 x i1> %t3
+}