Without this, a cloned instruction that takes full regs will trigger an
ir3_validate assert. This can happen, for ex, if an instruction that
writes p0.x and has a relative src gets cloned in ir3_sched.
Fixes an assert in Genshin Impact with a debug build.
Fixes:
9af795d9b98 ("ir3: Make ir3_instruction::address a normal register")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
*new_reg = *reg;
}
+ if (instr->address) {
+ assert(instr->srcs_count > 0);
+ new_instr->address = new_instr->srcs[instr->srcs_count - 1];
+ }
+
return new_instr;
}