int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
{
+ int ret = 0;
+
PHM_FUNC_CHECK(hwmgr);
- if (hwmgr->hwmgr_func->force_dpm_level != NULL)
- return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
+ if (hwmgr->hwmgr_func->force_dpm_level != NULL) {
+ ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
+ if (ret)
+ return ret;
+
+ if (hwmgr->hwmgr_func->set_power_profile_state) {
+ if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
+ ret = hwmgr->hwmgr_func->set_power_profile_state(
+ hwmgr,
+ &hwmgr->gfx_power_profile);
+ else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
+ ret = hwmgr->hwmgr_func->set_power_profile_state(
+ hwmgr,
+ &hwmgr->compute_power_profile);
+ }
+ }
- return 0;
+ return ret;
}
int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,