drm/i915/gt: Fixup misaligned function parameters
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 22 Jan 2021 19:29:07 +0000 (19:29 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 24 Mar 2021 18:30:35 +0000 (19:30 +0100)
Remember to align parameters to the '(', thanks checkpatch

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-4-chris@chris-wilson.co.uk
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
drivers/gpu/drm/i915/gt/intel_workarounds.c

index 9f8f8e4..d9fc953 100644 (file)
@@ -3349,8 +3349,8 @@ static int virtual_context_alloc(struct intel_context *ce)
 }
 
 static int virtual_context_pre_pin(struct intel_context *ce,
-                                    struct i915_gem_ww_ctx *ww,
-                                    void **vaddr)
+                                  struct i915_gem_ww_ctx *ww,
+                                  void **vaddr)
 {
        struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
 
index 912e020..0676239 100644 (file)
@@ -1111,11 +1111,10 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
        /* Wa_1607087056:icl,ehl,jsl */
        if (IS_ICELAKE(i915) ||
-               IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
+           IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
                wa_write_or(wal,
                            SLICE_UNIT_LEVEL_CLKGATE,
                            L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
-       }
 }
 
 static void