llvm-reduce: Add undef to new subregister IMPLICIT_DEFs
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 13 Sep 2022 18:22:58 +0000 (14:22 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 13 Sep 2022 22:10:56 +0000 (18:10 -0400)
This avoids a verifier error from the other unused lanes when
LiveIntervals is used.

llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp

index 590ea61..dd3ecd7 100644 (file)
@@ -5,7 +5,7 @@
 # CHECK-INTERESTINGNESS: V_ADD_U32
 
 # RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: undef %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
 # RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %{{[0-9]+}}.sub0, %{{[0-9]+}}.sub1, implicit $exec
 # RESULT-NEXT: S_ENDPGM 0, implicit %1
 
index c87d5eb..9b2a475 100644 (file)
@@ -128,8 +128,13 @@ static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
         bool IsGeneric = MRI->getRegClassOrNull(Reg) == nullptr;
         unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF
                                     : TargetOpcode::IMPLICIT_DEF;
+
+        unsigned State = getRegState(MO);
+        if (MO.getSubReg())
+          State |= RegState::Undef;
+
         BuildMI(*EntryMBB, EntryInsPt, DebugLoc(), TII->get(ImpDef))
-          .addReg(NewReg, getRegState(MO), MO.getSubReg());
+          .addReg(NewReg, State, MO.getSubReg());
       }
 
       // Update all uses.